Power system inhibit method and device and structure therefor
AssigneeSemiconductor Components Industries, LLC
InventorsJosef Halamik, Jefferson Hall
Life of this patent
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Abstract
A power control system (25) uses two separate currents to control a startup operation of the power control system (25). The two currents are shunted to ground to inhibit operation of the power control system (25) and one of the two currents is disabled to minimize power dissipation. The two independently controlled currents are generated by a multiple output current high voltage device (12) responsively to two separate control signals (23,24).
Claims20
A method of forming a high voltage multiple output current device comprising:
- providing a substrate of a first conductivity type;
- forming a first doped region of a second conductivity type on a first portion of the substrate including forming the first doped region as a first closed geometric shape having a center and a first periphery wherein a first portion of the first periphery has a first contour and a second portion of the first periphery has a second contour and also wherein the first doped region includes a drain and a source of a J-FET transistor, a drain of a first MOS transistor, and a drain of a second MOS transistor;
- forming on the substrate a second doped region of the second conductivity type having a second periphery wherein a portion of the second periphery is juxtaposed to the first portion of the first periphery and has a third contour that is shaped the same as the first contour and wherein the second doped region is a source of the first MOS transistor;
- and
- forming on the substrate a third doped region of the second conductivity type having a third periphery wherein a portion of the third periphery is juxtaposed to the second portion of the first periphery and has a fourth contour that is shaped the same as the second contour and wherein the third doped region is a source of the second MOS transistor.
A high voltage multiple output current device comprising:
- a substrate of a first conductivity type;
- a first doped region of a second conductivity type on a first portion the substrate, the first doped region formed as a first closed geometric shape having a center and a first periphery wherein a first portion of the first periphery has a first contour and a second portion of the first periphery has a second contour and also wherein the first doped region is a drain and a source of a J-FET transistor, a drain of a first MOS transistor, and a drain of a second MOS transistor;
- a second doped region of the second conductivity type on the substrate and having a second periphery wherein a portion of the second periphery is juxtaposed to the first portion of the first periphery and has a third contour that is the same shape as the first contour wherein the second doped region is a source of the first MOS transistor;
- and
- a third doped region of the second conductivity type on the substrate and having a third periphery wherein a portion of the third periphery is juxtaposed to the second portion of the first periphery and has a fourth contour that is the same shape as the second contour, and wherein the third doped region is a source of the second MOS transistor.
A power control system inhibition method comprising:
- generating a first output current at an output of a system controller responsive to a first value of an output voltage;
- and
- coupling the output to a voltage return to inhibit generation of the first output current.
Dependencies are inferred from the claim text.