Phase change memory cell with high read margin at low power operation
AssigneeInfineon Technologies AG
InventorThomas Happ
Life of this patent
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Abstract
A memory cell device includes a first electrode, phase-change material adjacent the first electrode, a second electrode adjacent the phase-change material, a diffusion barrier adjacent the phase-change material, and isolation material adjacent the diffusion barrier for thermally isolating the phase-change material. The diffusion barrier prevents diffusion of the phase-change material into the isolation material.
Claims29
1-7. (canceled)
A method for fabricating a memory cell device, the method comprising:
- providing a preprocessed wafer having a first electrode;
- depositing a phase-change material layer adjacent the preprocessed wafer;
- depositing an electrode material layer adjacent the phase-change material layer;
- etching the phase-change material layer and the electrode material layer to form a second electrode and a storage location;
- and
- depositing isolation material adjacent the storage location.
A method for fabricating a memory cell device, the method comprising:
- providing a preprocessed wafer having a first electrode;
- depositing an isolation material layer adjacent the preprocessed wafer;
- depositing a stop layer adjacent the isolation material layer;
- depositing a sacrificial layer adjacent the stop layer;
- etching the sacrificial layer to the stop layer to form a tapered via above the first electrode;
- etching the stop layer and the isolation layer at a bottom of the tapered via to form an extended via;
- removing the sacrificial layer;
- depositing phase-change material in the extended via;
- and
- fabricating a second electrode adjacent the phase-change material.
A method for fabricating an integrated circuit having a memory cell, the method comprising:
- providing a preprocessed wafer including a first electrode;
- depositing a resistivity changing material layer over the preprocessed wafer;
- depositing an electrode material layer over the resistivity changing material layer;
- etching the resistivity changing material layer and the electrode material layer to expose portions of the preprocessed wafer to provide a storage location and a second electrode;
- depositing a diffusion barrier material layer over exposed portions of the second electrode, the storage location, and the preprocessed wafer;
- depositing an isolation material layer over the diffusion barrier material layer;
- and
- planarizing the isolation material layer and the diffusion barrier material layer to expose the second electrode.
Dependencies are inferred from the claim text.