Wafer level chip packaging

A packaged microelectronic element, comprising:

• a microelectronic element including a device region and a contact region exposed at the front face, the contact region including a plurality of bond pads;
• a lid joined to the microelectronic element, the lid overlying the device region;
• a plurality of contacts exposed at a top surface of said packaged microelectronic element;
• and
• a plurality of conductive traces extending upwardly from said bond pads at least partly along walls of said packaged microelectronic element to said contacts.

A method of making a plurality of lidded microelectronic elements, comprising:

• (a) providing a device wafer having a front surface and a plurality of contacts on the front surface;
• (b) assembling an inner surface of a lid wafer to the front surface of the device wafer, the lid wafer including a first portion consisting essentially of inorganic material extending between the inner surface and an outer surface of the lid wafer and second portions including polymeric material disposed within openings in the first portion;
• (c) forming apertures extending through the second portions in alignment with said contacts;
• and
• (d) severing the assembled lid wafer and device wafer along dicing lanes into lidded microelectronic elements.