Image sensor and method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorJong-Wan Jung
Life of this patent
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Abstract
An image sensor may include a semiconductor substrate having a pixel array region and a logic region. A first gate electrode may be formed on the pixel array region of the semiconductor substrate. A lower electrode may be formed on a portion of the logic region of the semiconductor substrate. A first capping layer may be formed on at least a portion of the lower electrode. A dielectric layer may be formed on the first capping layer. An upper electrode may be formed on the dielectric layer. The first gate electrode and the lower electrode may include a polysilicon layer, and the first capping layer may include at least one of a metal layer and a metal silicide layer.
Claims20
An image sensor comprising:
- a semiconductor substrate having a pixel array region and a logic region;
- a first gate electrode formed on the pixel array region of the semiconductor substrate;
- a lower electrode formed on the logic region of the semiconductor substrate;
- a first capping layer formed on at least a portion of the lower electrode;
- a dielectric layer formed on the first capping layer;
- and
- an upper electrode formed on the dielectric layer,
- wherein the first gate electrode and the lower electrode include a polysilicon layer, and the first capping layer includes at least one of a metal layer and a metal silicide layer.
A method of fabricating an image sensor comprising:
- forming a polysilicon layer on a semiconductor substrate having a pixel array region and a logic region;
- forming a first capping layer on the polysilicon layer, the first capping layer including at least one of a metal layer and a metal silicide layer;
- forming a dielectric layer on the first capping layer;
- forming an upper electrode layer on the dielectric layer;
- patterning the upper electrode layer, the dielectric layer and the first capping layer to form an upper electrode, a dielectric film and a first capping film stacked on a portion of the polysilicon layer within the logic region of the semiconductor substrate;
- and
- patterning the polysilicon layer to form a first gate electrode in the pixel array region of the semiconductor substrate and a lower electrode interposed between the first capping film and the logic region of the semiconductor substrate.
Dependencies are inferred from the claim text.