Flip-flop circuit and frequency divider using the flip-flop circuit

A flip-flop circuit comprising:

• a first load element through which power supply current flows and that is connected between a first power supply potential and a first output terminal, the first output terminal and a second output terminal outputting complementary signals;
• a second load transistor that is connected between the first power supply potential and the second output terminal and whose conductive state is controlled by the signal of the first output terminal;
• a first latch portion that is connected between a second power supply potential different from the first power supply potential and the first and second output terminals, latches the signals of the first and second output terminals, and inverts the latched signals of the first and second output terminals by complementary first and second input pulses and complementary signals of first and second output nodes;
• a third load transistor that is connected between the first power supply potential and the first output node and whose conductive state is controlled by the signal of the second output node;
• a fourth load transistor that is connected between the first power supply potential and the second output node and whose conductive state is controlled by the signal of the first output node;
• and
• a second latch portion that is connected between the second power supply potential and the first and second output nodes, latches the signals of the first and second output nodes, and inverts the latched signals of the first and second output nodes by the first and second input pulses and the signals of the first and second output terminals.

A frequency divider comprising N stages (where N is an integer equal to or greater than 2) of cascade-connected circuit blocks comprising flip-flop circuits where latched complementary signals of first and second output terminals are inverted by complementary first and second input pulses, the frequency divider dividing the frequencies of the first and second input pulses into ½ N, wherein

• the circuit blocks comprise a first circuit block whose frequency is high and a second circuit block whose frequency is low,
• the first circuit block comprises a first flip-flop circuit,
• the first flip-flop circuit comprises
• a first load element through which power supply current flows and that is connected between a first power supply potential and a first output terminal, the first output terminal and a second output terminal outputting complementary signals,
• a second load element that is connected between the first power supply potential and the second output terminal and through which power supply current flows,
• a first latch portion that is connected between a second power supply potential different from the first power supply potential and the first and second output terminals, latches the signals of the first and second output terminals, and inverts the latched signals of the first and second output terminals by the first and second input pulses and complementary signals of first and second output nodes,
• a third load element that is connected between the first power supply potential and the first output node and through which power supply current flows,
• a fourth load element that is connected between the first power supply potential and the second output node and through which power supply current flows, and
• a second latch portion that is connected between the second power supply potential and the first and second output nodes, latches the signals of the first and second output nodes, and inverts the latched signals of the first and second output nodes by the first and second input pulses and the signals of the first and second output terminals,
• the second circuit block comprises a second flip-flop circuit, and
• the second flip-flop circuit comprises
• a fifth load element that is connected between the first output terminal and the first power supply potential and through which power supply current flows,
• a sixth load element that is connected between the first power supply potential and the second output terminal and through which power supply current flows,
• a first load transistor that is connected between the first power supply potential and the first output terminal and whose conductive state is controlled by the signal of the second output terminal,
• a second load transistor that is connected between the first power supply potential and the second output terminal and whose conductive state is controlled by the signal of the first output terminal,
• the first latch portion,
• a seventh load element that is connected between the first power supply potential and the first output node and through which power supply current flows,
• an eighth load element that is connected between the first power supply potential and the second output node and through which power supply current flows,
• a third load transistor that is connected between the first power supply potential and the first output node and whose conductive state is controlled by the signal of the second output node,
• a fourth load transistor that is connected between the first power supply potential and the second output node and whose conductive state is controlled by the signal of the first output node, and
• the second latch portion.

A frequency divider comprising N stages (where N is an integer equal to or greater than 2) of cascade-connected circuit blocks comprising flip-flop circuits where latched complementary signals of first and second output terminals are inverted by complementary first and second input pulses, the frequency divider dividing the frequencies of the first and second input pulses into ½ N, wherein

• the circuit blocks comprise a first circuit block whose frequency is high and a second circuit block whose frequency is low,
• the first circuit block comprises a first flip-flop circuit,
• the first flip-flop circuit comprises
• a first load element through which power supply current flows and that is connected between a first power supply potential and a first output terminal, the first output terminal and a second output terminal outputting complementary signals,
• a second load element that is connected between the first power supply potential and the second output terminal and through which power supply current flows,
• a first latch portion that is connected between a second power supply potential different from the first power supply potential and the first and second output terminals, latches the signals of the first and second output terminals, and inverts the latched signals of the first and second output terminals by the first and second input pulses and complementary signals of first and second output nodes,
• a third load element that is connected between the first power supply potential and the first output node and through which power supply current flows,
• a fourth load element that is connected between the first power supply potential and the second output node and through which power supply current flows, and
• a second latch portion that is connected between the second power supply potential and the first and second output nodes, latches the signals of the first and second output nodes, and inverts the latched signals of the first and second output nodes by the first and second input pulses and the signals of the first and second output terminals,
• the second circuit block comprises a second flip-flop circuit, and
• the second flip-flop circuit comprises
• a first load transistor that is connected between the first output terminal and the first power supply potential and whose conductive state is controlled by the signal of the second output terminal,
• a second load transistor that is connected between the first power supply potential and the second output terminal and whose conductive state is controlled by the signal of the first output terminal,
• the first latch portion,
• a third load transistor that is connected between the first power supply potential and the first output node and whose conductive state is controlled by the signal of the second output node,
• a fourth load transistor that is connected between the first power supply potential and the second output node and whose conductive state is controlled by the signal of the first output node, and
• the second latch portion.

A frequency divider comprising N stages (where N is an integer equal to or greater than 2) of cascade-connected circuit blocks comprising flip-flop circuits where latched complementary signals of first and second output terminals are inverted by complementary first and second input pulses, the frequency divider dividing the frequencies of the first and second input pulses into ½ N, wherein

• the circuit blocks comprise a first circuit block that operates at a high frequency, a second circuit block that operates at a low frequency, and a third circuit block that operates at an intermediate frequency,
• the first circuit block comprises a first flip-flop circuit,
• the first flip-flop circuit comprises
• a first load element through which power supply current flows and that is connected between a first power supply potential and a first output terminal, the first output terminal and a second output terminal outputting complementary signals,
• a second load element that is connected between the first power supply potential and the second output terminal and through which power supply current flows,
• a first latch portion that is connected between a second power supply potential different from the first power supply potential and the first and second output terminals, latches the signals of the first and second output terminals, and inverts the latched signals of the first and second output terminals by the first and second input pulses and complementary signals of first and second output nodes,
• a third load element that is connected between the first power supply potential and the first output node and through which power supply current flows,
• a fourth load element that is connected between the first power supply potential and the second output node and through which power supply current flows, and
• a second latch portion that is connected between the second power supply potential and the first and second output nodes, latches the signals of the first and second output nodes, and inverts the latched signals of the first and second output nodes by the first and second input pulses and the signals of the first and second output terminals,
• the second circuit block comprises a second flip-flop circuit,
• the second flip-flop circuit comprises
• a first load transistor that is connected between the first output terminal and the first power supply potential and whose conductive state is controlled by the signal of the second output terminal,
• a second load transistor that is connected between the first power supply potential and the second output terminal and whose conductive state is controlled by the signal of the first output terminal,
• the first latch portion,
• a third load transistor that is connected between the first power supply potential and the first output node and whose conductive state is controlled by the signal of the second output node,
• a fourth load transistor that is connected between the first power supply potential and the second output node and whose conductive state is controlled by the signal of the first output node, and
• the second latch portion,
• the third circuit block comprises a third flip-flop circuit, and
• the third flip-flop circuit comprises
• a fifth load element that is connected between the first output terminal and the first power supply potential and through which power supply current flows,
• a sixth load element that is connected between the first power supply potential and the second output terminal and through which power supply current flows,
• a fifth load transistor that is connected between the first power supply potential and the first output terminal and whose conductive state is controlled by the signal of the second output terminal,
• a sixth load transistor that is connected between the first power supply potential and the second output terminal and whose conductive state is controlled by the signal of the first output terminal,
• the first latch portion,
• a seventh load element that is connected between the first power supply potential and the first output node and through which power supply current flows,
• an eighth load element that is connected between the first power supply potential and the second output node and through which power supply current flows,
• a seventh load transistor that is connected between the first power supply potential and the first output node and whose conductive state is controlled by the signal of the second output node,
• an eighth load transistor that is connected between the first power supply potential and the second output node and whose conductive state is controlled by the signal of the first output node, and
• the second latch portion.