Reconfigurable logic block, programmable logic device provided with the reconfigurable logic block, and method of fabricating the reconfigurable logic block

A programmable logic device comprising a plurality of reconfigurable logic blocks arrayed in a matrix, a plurality of wires connecting said reconfigurable logic blocks, a plurality of switch blocks provided at intersections between said wires, a plurality of connection blocks provided between input-output lines of each of said reconfigurable logic blocks and said wires, and I/O blocks that perform input and output with respect to the exterior, wherein:

• each of said reconfigurable logic blocks comprises a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of said arithmetic circuit;
• and
• a plurality of different circuits are configured by changing the settings of predetermined signals in said first and second circuits.

A method of creating a reconfigurable logic block comprising a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of said arithmetic circuit, wherein:

• said reconfigurable logic block comprises a different circuit that causes changes in the settings of predetermined signals in said first and second circuits.

A method of configuring an ASIC by utilizing a method of creating a reconfigurable logic block comprising a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of said arithmetic circuit, wherein:

• said reconfigurable logic block comprises a different circuit that causes changes in the settings of predetermined signals in said first and second circuits;
• and
• the setting of predetermined signals in said first and second circuits is done by fixing the predetermined signals to a first power level or a second power level.