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US 2007/0186197 A1Published application
Design verification using formal techniques
AssigneeBroadcom Corporation
InventorYuan Lu
Life of this patent
Estimating the term…
Abstract
Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the design may be generated and model checking applied to the abstraction. Results obtained using these techniques may be extended by performance analysis and/or verification of sequential operations.
Claims20
A method of verifying a circuit design of a network switching logic block comprising:
- generating a reduced model of the circuit design of the network switching logic block;
- checking the reduced model by applying at least one property to the reduced model;
- generating at least one model of a sequential operation of the circuit design;
- and
- applying the at least one model to the reduced model to verify the circuit design.
2 more elements
An apparatus configured to:
- generate a reduced model of a circuit design of a network switching logic block;
- check the reduced model by applying at least one property to the reduced model;
- generate at least one model of a sequential operation of the circuit design;
- and
- apply the at least one model to the reduced model to verify the circuit design.
2 more elements
Dependencies are inferred from the claim text.