Techniques for providing greater error protection to error-prone bits in codewords genetated from irregular codes
AssigneeHitachi Global Technologies Netherlands B.V.
InventorsSizhen Yang, Yuan Lee, Shaohua Yang
Life of this patent
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Abstract
Greater error protection is provided to error-prone bits that are generated from irregular soft-decoded error correction codes. Error protection is increased to error-prone bits that of interest in a particular system (e.g., parity check bits). One or more extra bits are added to each codeword in the encoding process. The one or more extra bits correspond to lower weights. The one or more extra bits are discarded after each codeword is decoded.
Claims20
A system for correcting errors in data, the system comprising:
- a first encoder that encodes an input sequence using an irregular error correction code to generate an (n+m)-bit codeword for each set of k-bits in the input sequence;
- at least one second encoder that maps the n-bits in each codeword to a block of L-bits;
- at least one first decoder that maps each block of L-bits to a block of n-bits;
- a second decoder that receives m-bits and the blocks of n-bits from the at least one first decoder, the second decoder correcting errors in the n-bits using a soft-decision decoding process to regenerate the (n+m)-bit codewords;
- and
- a stripper block that removes the m-bits from each of the (n+m)-bit codewords.
A method for correcting errors, the method comprising:
- encoding k-bit blocks of an input sequence using a generator matrix obtained from the parity check matrix of an irregular error correction code to generate (n +m)-bit codewords, wherein each of the n-bits in the (n+m)-bit codewords corresponds to a column of the parity check matrix having a weight greater than a weight of any of the columns of the parity check matrix that correspond to the m-bits in the (n+m)-bit codewords;
- and
- encoding the n-bits in each of the (n+m)-bit codewords to generate blocks of L-bits;
- combining the blocks of L-bits with the m-bits in the (n+m)-bit codewords to generate (L+m)-bit words;
- decoding the L-bits to generate blocks of n-bits;
- decoding the blocks of n-bits and the m-bits to correct errors in the n-bits using a soft-decision decoding process;
- and
- removing the m-bits from the (n+m)-bit codewords to generate n-bit codewords.
A hard disk drive controller comprising:
- a first encoder that encodes an input sequence using an irregular error correction code to generate an (n+m)-bit codeword for each set of k-bits in the input sequence, wherein a second encoder maps the n-bits in each codeword to a block of L-bits, and a first decoder maps each block of L-bits to a block of n-bits;
- a second decoder that receives n-bits from the first decoder and that corrects errors in the n-bits using a soft-decision decoding process to regenerate the (n+m)-bit codewords;
- and
- a stripper block that removes the m-bits from each of the (n+m)-bit codewords to generate n-bit codewords.
The system defined in claim 18 wherein the first encoder encodes the data using an irregular RA LDPC code.
Dependencies are inferred from the claim text.