Processor system and methodology with background error handling feature
OwnerBrian Flachs, H. Hofstee +2inventors
InventorsBrian Flachs, H. Hofstee, John Liberty, Brad Michael
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Abstract
A processor system is disclosed that integrates error correcting code (ECC) detection and correction hardware within an memory management circuit. ECC hardware circuitry provides detection, correction and generation of ECC data bits in conjunction with memory data read and writes. The disclosed methodology permits the detection and correction of soft single bit errors read from local memory in-line while using read modify write DMA circuit logic to correct local memory data. The disclosed methodology provides local memory data error detection and correction in a background memory scrub process without the need for additional in-line data logic.
Claims20
A method of handling information in a processor system comprising:
- storing data words and respective associated error correction codes in a local memory coupled to a processor included in the processor system;
- retrieving, by an error detection and correction circuit, a selected data word and associated error code from the local memory;
- forwarding, by the error detection and correction circuit, the selected data word to the processor if the selected data word exhibits no error;
- correcting, by the error detection and correction circuit using in-line error correction, the selected data word if the selected data word exhibits a correctable error to provide a corrected data word that is sent to both the processor and the local memory;
- signaling, by the error detection and correction circuit, an uncorrectable error condition to an error controller if the selected data word exhibits an uncorrectable error;
- and
- initiating, by the error controller, out-of-line error correction operations to correct correctable errors.
A processor system comprising:
- a first processor;
- a local memory that stores data words and respective associated error correction codes local to the first processor;
- a system memory port for coupling to a system memory that stores data words and supplies data words to the local memory;
- direct memory address (DMA) circuitry coupling the local memory to the system memory port;
- error detection and correction circuitry, coupled to the local memory and the first processor and the DMA circuitry, that retrieves a selected data word from the local memory, the error correction and detection circuitry using in-line error correction to correct the selected data word if the selected data word exhibits a correctable error to provide a corrected data word that is sent to both the first processor and the local memory;
- and
- an error controller, coupled to the error detection and correction circuitry, that receives error information from the error detection and correction circuitry, the error controller initiating out-of-line error correcting operations to correct correctable errors indicated by the error information received from the error detection and correction circuitry.
An information handling system (IHS) comprising:
- a first processor;
- a local memory that stores data words and respective associated error correction codes local to the first processor;
- a system memory that stores data words and supplies data words to the local memory;
- direct memory address (DMA) circuitry coupling the local memory to the system memory;
- error detection and correction circuitry, coupled to the local memory and the first processor and the DMA circuitry, that retrieves a selected data word from the local memory, the error correction and detection circuitry using in-line error correction to correct the selected data word if the selected data word exhibits a correctable error to provide a corrected data word that is sent to both the first processor and the local memory;
- and
- an error controller, coupled to the error detection and correction circuitry, that receives error information from the error detection and correction circuitry, the error controller initiating out-of-line error correcting operations to correct correctable errors indicated by the error information received from the error detection and correction circuitry.
Dependencies are inferred from the claim text.