Testing of circuits with multiple clock domains

A method of testing a circuit under test with logic circuits and a scan chain comprising flip-flop cells with inputs and outputs operationally connected to the logic circuits, the circuit under test comprising a plurality of clock domains, each containing a respective part of the flip-flop cells that are clocked by a respective domain clock signal;

• the method comprising:
• selecting a set of test input patterns each with an associated combination of domain clock signals that will be selectively enabled to capture a response to the test pattern, wherein the set contains a particular test pattern that has the properties that:
• the response to the particular test pattern captured by a timing sensitive flip-flop cell in a first clock domain is used to detect a fault,
• the timing sensitive flip-flop cell receives data dependent on data from a source flip-flop cell that belongs to a second clock domain different from the first clock domain,
• the combination of selectively enabled domain clock signals associated with the particular test pattern comprises the clocks of both the first and second domain,
• the particular test pattern also having the further property that the data value in the source flip-flop cell is identical to a response value captured by the source flip-flop cell for the particular test pattern;
• switching the circuit under test to a test mode,
• supplying successive test input patterns from said set through the scan chain, including the particular test pattern;
• selectively enabling the combination of domain clock signals associated with each test pattern to capture a response of the logic circuits to the test pattern into flip-flop cells of the scan chain,
• using the captured response from at least part of the flip-flop cells to detect faults in the circuit under test, including the response captured by the timing sensitive flip-flop cell in response to the particular test pattern.

A medium carrying a set of test patterns for testing a circuit under test with logic circuits and a scan chain comprising flip-flop cells with inputs and outputs operationally connected to the logic circuits, the circuit under test including a plurality of clock domains, each containing a respective part of the flip-flop cells that are clocked by a respective domain clock signal;

• each of the set of test input patterns being associated with an associated combination of domain clock signals that will be selectively enabled to capture a response to the test pattern, wherein the set contains a particular test pattern that has the properties that:
• the response to the particular test pattern captured by a timing sensitive flip-flop cell in a first clock domain is used to detect a fault,
• the timing sensitive flip-flop cell receives data dependent on data from a source flip-flop cell that belongs to a second clock domain different from the first clock domain,
• the combination of selectively enabled domain clock signals associated with the particular test pattern comprises the clocks of both the first and second domain,
• the particular test pattern also having the further property that the data value in the source flip-flop cell is identical to a response value captured by the source flip-flop cell for the particular test pattern.

A method of generating a set of test patterns for a circuit under test with logic circuits and a scan chain comprising flip-flop cells with inputs and outputs operationally connected to the logic circuits, the circuit under test including a plurality of clock domains, each containing a respective part of the flip-flop cells that are clocked by a respective domain clock signal;

• each test pattern being an associated combination of domain clock signals that will be selectively enabled to capture a response to the test pattern, the method comprising:
• receiving information representing an original design that corresponds to the circuit under test;
• including with each pattern clock status signals that indicate whether respective ones of the domain clocks will be disabled during capture of a response to the pattern;
• generating an adapted version of the original design wherein additional logic circuits have been added to the original design, the additional logic circuits being designed to selectively enable a dependence of an input signal of the timing sensitive flip-flop cell on data from the source flip-flop cell according to the original design, when the clock status signals indicate that the second domain clock is disabled, the additional circuits also being designed to enable the dependence when the input and output signals of the source flip-flop cell are identical and the second domain clock is enabled;
• selecting the set of test patterns with associated clock status signals for the adapted version so that a set of logic circuit faults is covered for the adapted version.

A test pattern generating machine for generating a set of test patterns for a circuit under test with logic circuits and a scan chain comprising flip-flop cells with inputs and outputs operationally connected to the logic circuits, the circuit under test comprising a plurality of clock domains, each containing a respective part of the flip-flop cells that are clocked by a respective domain clock signal;

• each test pattern being an associated combination of domain clock signals that will be selectively enabled to capture a response to the test pattern, the machine being arranged to:
• receive information representing an original design that corresponds to the circuit under test;
• include with each pattern clock status signals that indicate whether respective ones of the domain clocks will be disabled during capture of a response to the pattern;
• generating an adapted version of the original design wherein additional logic circuits have been added to the original design, the additional logic circuits being designed to selectively enable a dependence of an input signal of the timing sensitive flip-flop cell on data from the source flip-flop cell according to the original design, when the clock status signals indicate that the second domain clock is disabled, the additional circuits also being designed to enable the dependence when the input and output signals of the source flip-flop cell;
• selecting the set of test patterns with associated clock status signals for the adapted version so that a set of logic circuit faults is covered for the adapted version.

A computer program product containing machine instructions for generating a set of test patterns for a circuit under test with logic circuits and a scan chain comprising flip-flop cells with inputs and outputs operationally connected to the logic circuits, the circuit under test comprising a plurality of clock domains, each containing a respective part of the flip-flop cells that are clocked by a respective domain clock signal;

• each test pattern being an associated combination of domain clock signals that will be selectively enabled to capture a response to the test pattern, the instructions being arranged to:
• receive information representing an original design that corresponds to the circuit under test;
• include with each pattern clock status signals that indicate whether respective ones of the domain clocks will be disabled during capture of a response to the pattern;
• generating an adapted version of the original design wherein additional logic circuits have been added to the original design, the additional logic circuits being designed to selectively enable a dependence of an input signal of the timing sensitive flip-flop cell on data from the source flip-flop cell according to the original design, when the clock status signals indicate that the second domain clock is disabled, the additional circuits also being designed to enable the dependence when the input and output signals of the source flip-flop cell are identical and the second domain clock is enabled;
• selecting the set of test patterns with associated clock status signals for the adapted version so that a set of logic circuit faults is covered for the adapted version.