Low cost imbedded load board diagnostic test fixture
AssigneeTexas Instruments Incorporated
InventorCorey Goodrich
Life of this patent
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Abstract
In a method and system for testing an intermediary device, a tester provides a test signal to a device under test (DUT) via a first circuit path on the intermediary device. A first response is received from the DUT to verify that the DUT and the first circuit path are substantially free from defects. The DUT is configured to include a second circuit path to be tested. The test signal is provided by the DUT to the second circuit path. A second response is received from the DUT to verify that the second circuit path is substantially free from defects. In a similar manner, the DUT is configured to include additional components of the intermediary device to be tested.
Claims20
A test system for testing an intermediary device, the test system comprising:
- a tester coupled to the intermediary device, the tester being operable to provide a test signal;
- and
- a device under test (DUT) electrically coupled to the intermediary device, wherein the intermediary device includes a plurality of circuit paths for communicating the test signal, wherein the DUT is configurable to include a predefined circuit path of the plurality of circuit paths, wherein the DUT is operable to provide the test signal to the predefined circuit path to verify continuity.
A method for testing an intermediary device coupled to a device under test (DUT), the method comprising:
- providing a test signal to the DUT via a first circuit path on the intermediary device;
- receiving a first response from the DUT to verify that the DUT is substantially free from defects;
- configuring the DUT to include a second circuit path on the intermediary device, wherein the second circuit path is coupled in series with the first circuit path;
- providing the test signal to the DUT, wherein the DUT provides the test signal to the second circuit path;
- and
- receiving a second response from the DUT to verify that the second circuit path is substantially free from defects.
A method for testing a relay included on an intermediary device, the intermediary device being coupled to a device under test (DUT), the method comprising:
- placing the DUT in a test mode;
- closing the relay to enable a loop back path;
- configuring a boundary scan chain for the DUT, wherein the boundary scan chain originates with a TDI input and terminates with a TDO output, wherein the relay is coupled to the boundary scan chain via a primary output and a primary input;
- providing a predefined logic signal to the TDI input;
- and
- verifying whether the predefined logic signal is received at the TDO output.
Dependencies are inferred from the claim text.