Circuit and method for loop control
AssigneeNEC Electronics Corporation
InventorSatoshi Chiba
Life of this patent
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Abstract
A loop control circuit of the present invention includes a program counter for sequentially indicating an address of an instruction, a LSA calculation circuit for calculating a loop start address of a loop start instruction, a LEA calculation circuit for calculating a loop end address of a loop end instruction, an interlock generation circuit for generating an interlock until a pipeline of a loop instruction is completed so as to suspend a pipeline process of the loop end instruction, and a loop end evaluation circuit for setting the program counter to the loop start address according to a result of a comparison between the program counter and the loop end address after the pipeline process of the loop instruction is completed.
Claims20
A loop control circuit to control to repeatedly execute from a loop start instruction to a loop end instruction according to a loop instruction in a processor to process an instruction in a pipeline, the loop control circuit comprising:
- an interlock generation circuit to suspend a pipeline process of the loop end instruction until a pipeline process of the loop instruction is completed;
- a loop end evaluation circuit to take a loop end evaluation when the pipeline process of the loop end instruction is executed.
A loop control circuit to control to repeatedly execute from a loop start instruction to a loop end instruction according to a loop instruction in a processor to process an instruction in a pipeline, the loop control circuit comprising:
- a program counter to sequentially indicate an address of an instruction to be processed in pipeline;
- a loop end address calculation circuit to calculate a loop end address, the loop end address being an address of the loop end instruction;
- and
- an interlock generation circuit to generate an interlock according to a result of a comparison between the program counter and the loop end address until a completion of the pipeline process of the loop instruction so as to suspend the pipeline process of the loop end instruction.
A loop control method to control to repeatedly execute from a loop start instruction to a loop end instruction according to a loop instruction in a processor to process an instruction in a pipeline, the loop control method comprising:
- generating an interlock to suspend a pipeline process of the loop end instruction until a pipeline process of the loop instruction is completed.
Dependencies are inferred from the claim text.