Pipelined processor and instruction loop execution method

Abstract

Processor (10) having a processing pipeline (100) is extended with an arrangement to reduce the loss of cycles associated with loop execution in pipeline (100). Loop start detection until (116a) detects a loop start instruction containing information about the loop count and last instruction in the loop information about the first instruction in the loop is also present. Loop end detection until (114a) is provided with the loop end information, and fetch stage (112) is provided with the loop start information by loop start detection until (116a). Upon detection of a loop end, loop end detection until (114a) generates detection tags labeling the content of pipeline (100) which are evaluated by tag detection until (144). Loop execution control stage (142) compares the loop count information with detection information generated by tag detection until (144) and, if necessary, removes superfluous instructions from pipeline (100).

Dependencies are inferred from the claim text.