Supporting out-of-order issue in an execute-ahead processor

An apparatus for out-of-order issue in a processor, comprising:

• a memory coupled to the processor, wherein data and instructions used during the operation of the processor are stored in and retrieved from the memory;
• an in-order execution mechanism on the processor;
• an issue queue with an entry for each of a plurality of pipelines on the processor;
• wherein the execution mechanism is configured to issue instructions from the issue queue to the pipelines in program order during a normal-execution mode;
• while issuing the instructions, the execution mechanism is configured to determine if any instruction in the issue queue has an unresolved short-latency data dependency which depends on a short-latency operation;
• and
• if so, the execution mechanism is configured to generate a checkpoint and enter an out-of-order-issue mode, wherein instructions in the issue queue with unresolved short-latency data dependencies are held and not issued, and wherein other instructions in the issue queue without unresolved data dependencies are allowed to issue out-of-order.

A computer system that performs out-of-order issue in a processor, comprising:

• a memory coupled to the processor, wherein data and instructions used during the operation of the processor are stored in and retrieved from the memory;
• an in-order execution mechanism on the processor;
• an issue queue with an entry for each of a plurality of pipelines on the processor;
• wherein the execution mechanism is configured to issue instructions from the issue queue to the pipelines in program order during a normal-execution mode;
• while issuing the instructions, the execution mechanism is configured to determine if any instruction in the issue queue has an unresolved short-latency data dependency which depends on a short-latency operation;
• and
• if so, the execution mechanism is configured to generate a checkpoint and enter an out-of-order-issue mode, wherein instructions in the issue queue with unresolved short-latency data dependencies are held and not issued, and wherein other instructions in the issue queue without unresolved data dependencies are allowed to issue out-of-order.