Mechanism to minimize unscheduled D-cache miss pipeline stalls
AssigneeInternational Business Machines Corporation
InventorDavid Luick
Life of this patent
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Abstract
A method and apparatus for minimizing unscheduled D-cache miss pipeline stalls is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The method includes receiving an issue group of instructions, determining if a first instruction in the issue group is a load instruction, and if so, scheduling the first instruction to be executed in a pipeline in which execution is not delayed with respect to another pipeline in the cascaded delayed execution pipeline unit.
Claims20
A method of scheduling execution of an instruction in a processor having at least one cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other, the method comprising:
- receiving an issue group of instructions;
- determining if a first instruction in the issue group is a load instruction;
- and
- if so, scheduling the first instruction to be executed in a pipeline in which execution is not delayed with respect to another pipeline in the cascaded delayed execution pipeline unit.
An integrated circuit device comprising:
- a cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other;
- circuitry configured to:
- receive an issue group of instructions;
- determine if a first instruction in the issue group is a load instruction;
- and
- if so, schedule the first instruction to be executed in a pipeline in which execution is not delayed with respect to another pipeline in the cascaded delayed execution pipeline unit.
A processor comprising:
- a level two cache;
- a level one cache;
- a cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other;
- predecoder circuitry configured to:
- receive from the level two cache a group of instructions to be issued as an issued group;
- determine if a first instruction in the group of instructions is a load instruction;
- if so, schedule the first instruction to be executed in a pipeline in which execution is not delayed with respect to another pipeline in the cascaded delayed execution pipeline unit;
- and
- send the group of instructions to the level one cache.
Dependencies are inferred from the claim text.