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US 2007/0186078 A1Published application
Integrated Circuit Device
AssigneeIpflex Inc.
InventorsKenji Ikeda, Hiroshi Shimura, Tomoyoshi Sato
Life of this patent
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AssigneeIpflex Inc.
InventorsKenji Ikeda, Hiroshi Shimura, Tomoyoshi Sato
Estimating the term…
An integrated circuit device with a data processing block is provided, the data processing block including a plurality of operation units that are arranged in a matrix, a plurality of first wire sets that extend in a first direction in the matrix and transfer input data of each operation unit, a plurality of second wire sets that extend in a second direction in the matrix and transfer output data of each operation unit, and a plurality of switching units that are arranged at each intersection between the first and second wire sets and can select and connect any wire in the first wire sets and any wire in the second wire sets. The plurality of operation units include a plurality of types of operation units with different data paths that are suited to special-purpose processing, with an arrangement of operation units of the same type in the first direction or the second direction being formed in at least part of the data processing block. The functioning of the integrated circuit device can be dynamically changed by changing the configuration of the operation units and the integrated circuit device is composed of operation units with different data paths that are suited to special-purpose processing so that the integrated circuit device is both compact and economical.
1-41. (canceled)
An integrated circuit device comprising a data processing block including a first matrix and a second matrix, the first matrix and the second matrix respectively including a plurality of types of operation units and a wiring group for connecting the plurality of types of operation units, a configuration of data processing with the plurality of types of operation units being changeable by changing a route of the wiring group for data supplying to the plurality of types of operation units,
A method of designing an integrated circuit device that includes a data processing block in which a first matrix and a second matrix are included, the first matrix and the second matrix respectively including a plurality of types of operation units and a wiring group, a configuration of data processing with the plurality of types of operation units being changeable by changing a route of the wiring group, the plurality of types of operation units including a delay type operation unit that includes a data path suited to processing for delaying a transfer time of data, a plurality of the delay type operation units being arranged so as to connect the wiring group of the first matrix and the wiring group of the second matrix via at least one of the plurality of the delay type operation units,
Dependencies are inferred from the claim text.