Back to results
US 2007/0186076 A1Published application
Data pipeline transport system
OwnerAnthony Jonesinventor
Life of this patent
Estimating the term…
Abstract
A series of pipeline stages are interconnected with other similar stages in arbitrary topologies. Data travel is controlled and regulated by forward and back-pressure mechanisms.
Claims39
A data pipeline element, comprising:
- a data register and subordinate data register to independently store data words;
- a first protocol register to store a value to indicate the existence of a consumable data value in the data register;
- and
- a subordinate first protocol register to store a value to indicate the existence of a consumable data value in the subordinate data register;
- and
- a second protocol register having an input coupled to the data register and the first protocol register, and having an output coupled to the subordinate data register and the subordinate first protocol register;
- wherein at least two of the registers in the pipeline element are edge triggered and are updated on the same edge of a clock signal.
4 more elements
A data pipeline element, comprising:
- a data register and subordinate data register to independently store data words;
- a first protocol register to store a value to indicate the existence of a consumable data value in the data register;
- and
- a subordinate first protocol register to store a value to indicate the existence of a consumable data value in the subordinate data register;
- and
- a second protocol register having an input coupled to the data register and the first protocol register, and having an output coupled to the subordinate data register and the subordinate protocol register;
- wherein a signal path of an input signal for the subordinate data register has a different logical structure than a signal path of an input signal for the subordinate protocol register.
4 more elements
A pipeline element, comprising:
- a first clock signal and a second clock signal having time distinct phases that do not overlap;
- a master data latch and slave data latch to independently store data words;
- a master first protocol latch to store a value to indicate the existence of a consumable data value in the master data latch;
- a slave first protocol latch to store a value to indicate the existence of a consumable data value in the slave data latch;
- and
- a master second protocol latch and a slave second protocol latch to each store an enable indicator to indicate that a subsequent pipeline element will consume the value stored in the slave data latch;
- wherein the master data latch and slave data latches are clocked by clock signals combined with an enable signal, and wherein the master first protocol latch and the slave first protocol latch are respectively clocked directly by one of the two clock signals.
4 more elements
A pipeline element for a bidirectional data pipeline, comprising:
- a first clock signal and a second clock signal having time distinct phases that do not overlap;
- a master forward data latch and slave forward data latch to independently store data words;
- a master reverse data latch and slave reverse data latch to independently store data words;
- a master first protocol latch and a slave first protocol latch to each store a respective signal to indicate data transfer may proceed in the forward direction;
- and
- a master second protocol latch and a slave second protocol latch to each store a respective signal to indicate data transfer may proceed in the reverse direction.
3 more elements
A pipeline element in a bi-directional data pipeline, comprising:
- a first clock signal and a second clock signal having phases that do not overlap;
- a set of two forward data master-slave latches;
- a set of two reverse data master-slave latches;
- a set of two forward protocol master-slave latches;
- and
- a set of two reverse protocol master-slave latches;
- wherein the master latches may change their state only at a rising edge of the first clock signal, and wherein the slave latches may change their state only at a rising edge of the second clock signal.
4 more elements
A method for moving data along a bi-directional data pipeline, comprising:
- storing a reverse-flow signal in a master first protocol latch during a first clock phase;
- moving the reverse flow signal to a slave first protocol latch during a second clock phase, the second clock phase not overlapping the first clock phase;
- storing a forward flow signal in a master second protocol latch during the first clock phase;
- moving the forward flow signal in a slave second protocol latch during the second clock phase;
- storing data into a forward data master latch during the first clock phase if an output signal from the slave second protocol latch is asserted;
- and
- storing data into a reverse data master latch during the first clock phase if an output signal from the slave first protocol latch is asserted.
4 more elements
Dependencies are inferred from the claim text.