D-cache miss prediction and scheduling
AssigneeInternational Business Machines Corporation
InventorDavid Luick
Life of this patent
Estimating the term…
Abstract
A method and apparatus for D-cache miss prediction and scheduling is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The method includes receiving an issue group of instructions, determining if a first instruction in the issue group resulted in a cache miss during a previous execution of the first instruction, and if so, scheduling the first instruction to be executed in a pipeline in which execution is delayed with respect to another pipeline in the cascaded delayed execution pipeline unit.
Claims20
A method of scheduling execution of an instruction in a processor having at least one cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other, the method comprising:
- receiving an issue group of instructions;
- determining if a first instruction in the issue group resulted in a cache miss during a previous execution of the first instruction;
- and
- if so, scheduling the first instruction to be executed in a pipeline in which execution is delayed with respect to another pipeline in the cascaded delayed execution pipeline unit.
An integrated circuit device comprising:
- a cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other;
- circuitry configured to:
- receive an issue group of instructions;
- determine if a first instruction in the issue group resulted in a cache miss during a previous execution of the first instruction;
- and
- if so, schedule the first instruction to be executed in a pipeline in which execution is delayed with respect to another pipeline in the cascaded delayed execution pipeline unit.
An integrated circuit device comprising:
- a cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other;
- circuitry configured to:
- receive an issue group of instructions;
- determine if a first instruction in the issue group resulted in a cache miss during a previous execution of the first instruction;
- and
- if so:
- schedule the first instruction to be executed in a first pipeline in which execution is delayed less with respect to a second pipeline in the cascaded delayed execution pipeline unit.
Dependencies are inferred from the claim text.