Optimizing data bandwidth across a variable asynchronous clock domain
AssigneeInternational Business Machines Corporation
InventorsMark Bellows, Brian McKevett, Tolga Ozguner
Life of this patent
Estimating the term…
Abstract
Embodiments of the present invention optimize data bandwidth across an asynchronous buffer in a system with a variable clock domain. A move signal may be asserted to transfer data associated with a command into the asynchronous buffer. After the data has been moved into the buffer, an acknowledge signal may indicate that the transfer is complete. A launch signal may transfer the data in the asynchronous buffer to memory. Embodiments of the present invention allow the processing of a next command to begin at the earliest possible time while data associated with a previous command is being transferred into and out of the buffer, thereby increasing throughput and improving performance.
Claims20
A memory controller, comprising:
- (i) an asynchronous buffer configured to receive data at a first clock frequency and send data at a second clock frequency;
- (ii) command control logic configured to select, for processing, a command from one or more lists of commands in response to receiving a data request signal, and issue a valid signal indicating a command is available for processing;
- and
- (iii) a data flow controller configured to request a command from the command control logic, initiate transfer of data associated with a command into the asynchronous buffer in response to receiving the valid signal by asserting a move signal, receive an acknowledge indicating that the data has been transferred into the asynchronous buffer, assert a launch signal to transfer the data out of the asynchronous buffer, and to request data for a next command, assert the data request signal in a time period, beginning at the assertion of the data valid signal for the command, that is shorter than a first time period, wherein the first time period is the sum of the time period required to assert the move signal for the command and the time period to acknowledge that the data has been moved.
A method for transferring data across an asynchronous write buffer, comprising:
- for a first command, asserting a move signal, wherein the move signal initiates the transfer of data associated with the first command into the asynchronous buffer at a first clock frequency;
- asserting a launch signal, wherein the launch signal initiates the transfer of the data associated with the first command out of the asynchronous buffer at a second clock frequency;
- requesting data for a second command in a time period, beginning at the assertion of the data valid signal for the first command, that is shorter than a first time period, wherein the first time period is the sum of the time period to assert the move signal the and the time to acknowledge that the data has been moved.
A system, comprising:
- memory driven by a constant memory clock;
- a processor driven by a variable processor clock, configured to issue read and write commands to the memory;
- a clock controller configured to issue a request for changing the frequency of the processor clock, and change the frequency of the processor clock;
- and
- a memory controller comprising:
- (i) an asynchronous buffer configured to receive data at a first clock frequency and send data at a second clock frequency;
- (ii) command control logic configured to select, for processing, a command from one or more lists of commands in response to receiving a data request signal, and issue a valid signal indicating a command is available for processing;
- and
- (iii) a data flow controller configured to request a command from the command control logic, initiate transfer of data associated with a command into the asynchronous buffer in response to receiving the valid signal by asserting a move signal, receive an acknowledge indicating that the data has been transferred into the asynchronous buffer, assert a launch signal to transfer the data out of the asynchronous buffer, and to request data for a next command, assert the data request signal in a time period, beginning at the assertion of the data valid signal for the command, that is shorter than a first time period, wherein the first time period is the sum of the time period required to assert the move signal and the time period to acknowledge that the data has been moved.
Dependencies are inferred from the claim text.