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US 2007/0186060 A1Published application
Method and apparatus for exploiting parallelism across multiple traffic streams through a single channel
AssigneeIntel Corporation
InventorsRaman Nayyar, Suvansh Kapour
Life of this patent
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Abstract
Methods of obtaining, enqueueing and executing several memory transactions are described, where the memory transactions may be generated in a first order but executed in a second order. Despite the relaxed ordering, essential programming paradigms such as producer-consumer relationships are not affected. Chipsets and systems using the methods are also described and claimed.
Claims25
A method comprising:
- obtaining a plurality of memory transactions in a first order, each transaction to be associated with a logical identifier;
- enqueuing each memory transaction on one of a plurality of work queues, the work queue to be selected based on a type of the memory transaction and the logical identifier of the memory transaction;
- and
- executing the plurality of memory transactions in a second order.
1 more element
A chipset comprising:
- a plurality of targets to generate memory transactions;
- a virtualization engine to associate a logical stream with a memory transaction;
- a bus interface unit to issue memory transactions to a cache controller;
- and
- queueing logic to preserve an ordering relationship between a plurality of generated memory transactions and a plurality of issued memory transactions.
2 more elements
A system comprising:
- a memory;
- a cache controller to maintain data coherency between the memory and a cache;
- a plurality of peripheral devices;
- and
- a hub to exchange data between the memory and the plurality of peripheral devices;
- wherein
- a plurality of memory transactions from a peripheral device are generated in a first order;
- and
- the plurality of memory transactions are executed in a second order.
6 more elements
A computer-readable medium containing instructions to cause a processor to perform operations comprising:
- receiving a plurality of memory requests in a first order;
- sorting the memory requests according to a type and a group of the request;
- queueing the sorted memory requests on a plurality of queues for later execution;
- and
- executing a memory request from one of the plurality of queues.
2 more elements
Dependencies are inferred from the claim text.