Hardware acceleration for a software transactional memory system
OwnerBratin Saha, Ali-Reza Adl-Tabatabai +1inventors
InventorsBratin Saha, Ali-Reza Adl-Tabatabai, Quinn Jacobson
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OwnerBratin Saha, Ali-Reza Adl-Tabatabai +1inventors
InventorsBratin Saha, Ali-Reza Adl-Tabatabai, Quinn Jacobson
Estimating the term…
A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines reference by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an access is the first access to a shared memory line during a pendancy of a transaction. Additionally, in an aggressive operational mode version numbers representing versions of elements stored in shared memory lines are not stored and validated upon commitment to save on validation cost. Moreover, even in a cautious mode, that stores version numbers to enable validation, validation costs may not be incurred, if eviction of accessed shared memory lines do not occur during execution of the transaction.
An apparatus comprising:
An apparatus comprising:
A system comprising:
A method comprising:
A method comprising:
Dependencies are inferred from the claim text.