Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level

An apparatus that enforces memory reference ordering requirements at a Level 1 (L1) cache in a multiprocessor, comprising:

• a processor which is coupled to the L1 cache;
• wherein if the L1 cache receives an invalidation signal for a cache line while the processor is executing instructions in a speculative-execution mode, and if the cache line exists in the L1 cache, the apparatus is configured to,
• examine a load-mark in the cache line, wherein the load-mark being set indicates that the cache line has been loaded from during the speculative-execution mode, and
• if the load-mark is set, to cause the processor to fail the speculative-execution mode and to resume a normal-execution mode from a checkpoint, whereby failing the speculative-execution mode ensures that a potential update to the cache line indicated by the invalidation signal will not cause the memory reference ordering requirements to be violated during the speculative-execution mode.

A multiprocessor system that enforces memory reference ordering requirements at a Level 1 (L1) cache, comprising:

• a plurality of processors;
• a shared memory coupled to the plurality of processors;
• wherein a given processor within the plurality of processors is coupled to the L1 cache;
• wherein if the L1 cache receives an invalidation signal for a cache line at while the given processor is executing instructions in a speculative-execution mode, and if the cache line exists in the L1 cache, the L1 cache is configured to,
• examine a load-mark in the cache line, wherein the load-mark being set indicates that the cache line has been loaded from during the speculative-execution mode, and
• if the load-mark is set, to cause the given processor to fail the speculative-execution mode and to resume a normal-execution mode from a checkpoint, whereby failing the speculative-execution mode ensures that a potential update to the cache line indicated by the invalidation signal will not cause the memory reference ordering requirements to be violated during the speculative-execution mode.