Methods and apparatus for reducing command processing latency while maintaining coherence

A method of processing commands, comprising:

• providing a system comprising a plurality of chips;
• providing a memory map including memory addresses available to the system;
• and
• arranging the memory addresses into a plurality of groups so that:
• a first of the plurality of groups corresponds to a subset of memory addresses associated with a first chip in the system;
• and
• if a coherent command from a bus unit in the first chip requires access to a memory address in the first group, the coherent command is treated as non-coherent.

An apparatus for processing commands, comprising:

• logic adapted to store a memory map including memory addresses available to a system comprising a plurality of chips;
• wherein the memory addresses are arranged into a plurality of groups so that:
• a first of the plurality of groups corresponds to a subset of memory addresses associated with a first chip in the system;
• and
• if a coherent command from a bus unit in the chip requires access to a memory address in the first group, the coherent command is treated as non-coherent.

A computer program product, comprising:

• a medium readable by a computer, the computer readable medium having computer program code adapted to:
• provide a memory map including memory addresses available to a system comprising a plurality of chips;
• and
• arrange the memory addresses into a plurality of groups so that:
• a first of the plurality of groups corresponds to a subset of memory addresses associated with a first chip in the system;
• and
• if a coherent command from a bus unit in the first chip requires access to a memory address in the first group, the coherent command is treated as non-coherent.

A system for processing commands, comprising:

• a plurality of chips;
• a plurality of bus units, wherein two or more of the bus units may be on different chips, cards or computers of the system;
• a plurality of buses coupling the bus units;
• a plurality of memories, each of which corresponds to one or more of the bus units;
• and
• logic adapted to store a memory map including memory addresses available to the system;
• wherein the memory addresses are arranged into a plurality of groups so that:
• a first group of the plurality of groups corresponds to a subset of memory addresses associated with a first chip in the system;
• and
• if a coherent command from a bus unit in the first chip requires access to a memory address in the first group, the coherent command is treated as non-coherent.