Self prefetching L2 cache mechanism for data lines
AssigneeInternational Business Machines Corporation
InventorDavid Luick
Life of this patent
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Abstract
Embodiments of the present invention provide a method and apparatus for prefetching instruction lines. In one embodiment, the method includes fetching a first instruction line from a level 2 cache, extracting, from the first instruction line, an address identifying a first data line containing data targeted by a data access instruction contained in the first instruction line or a different instruction line; and prefetching, from the level 2 cache, the first data line using the extracted address.
Claims34
A method of prefetching data lines, comprising:
- (a) fetching a first instruction line from a level 2 cache;
- (b) extracting, from the first instruction line, an address identifying a first data line containing data targeted by a data access instruction contained in the first instruction line or a different instruction line;
- and
- (c) prefetching, from the level 2 cache, the first data line using the extracted address.
A processor comprising:
- a level 2 cache;
- a level 1 cache configured to receive instruction lines from the level 2 cache, wherein each instruction line comprises one or more instructions;
- a processor core configured to execute instructions retrieved from the level 1 cache;
- and
- circuitry configured to:
- (a) fetch a first instruction line from a level 2 cache;
- (b) identify, in the first instruction line, an address identifying a first data line containing data targeted by a data access instruction contained in the first instruction line or a different instruction line;
- and
- (c) prefetch, from the level 2 cache, the first data line using the extracted address.
A method of storing data target addresses in an instruction line, the method comprising:
- executing one or more instructions in the instruction line;
- determining if the one or more instructions accesses data in a data line and results in a cache miss;
- and
- if so, storing a data target address corresponding to the data line in a location which is accessible by a prefetch mechanism.
Dependencies are inferred from the claim text.