Self prefetching L2 cache mechanism for instruction lines
AssigneeInternational Business Machines Corporation
InventorDavid Luick
Life of this patent
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Abstract
Embodiments of the present invention provide a method and apparatus for prefetching instruction lines. In one embodiment, the method includes fetching a first instruction line from a level 2 cache, identifying, in the first instruction line, a branch instruction targeting an instruction that is outside of the first instruction line, extracting an address from the identified branch instruction, and prefetching, from the level 2 cache, a second instruction line containing the targeted instruction using the extracted address.
Claims24
A method of prefetching instruction lines, comprising:
- (a) fetching a first instruction line from a level 2 cache;
- (b) identifying, in the first instruction line, a branch instruction targeting an instruction that is outside of the first instruction line;
- (c) extracting an address from the identified branch instruction;
- and
- (d) prefetching, from the level 2 cache, a second instruction line containing the targeted instruction using the extracted address.
A processor comprising:
- a level 2 cache;
- a level 1 cache configured to receive instruction lines from the level 2 cache, wherein each instruction line comprises one or more instructions;
- a processor core configured to execute instructions retrieved from the level 1 cache;
- and
- circuitry configured to:
- (a) fetch a first instruction line from a level 2 cache;
- (b) identify, in the first instruction line, a branch instruction targeting an instruction that is outside of the first instruction line;
- (c) extract an address from the identified branch instruction;
- and
- (d) prefetch, from the level 2 cache, a second instruction line containing the targeted instruction using the extracted address.
A method of storing exit branch addresses in an instruction line, wherein the instruction line comprises one or more instructions, the method comprising:
- executing one of the one or more instructions in the instruction line;
- determining if the one of one or more of the instructions branches to an instruction in another instruction line;
- and
- if so, appending an exit address to the instruction line corresponding to the other instruction line.
Dependencies are inferred from the claim text.