Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modes
AssigneeInternational Business Machines Corporation
InventorsJohn Irish, Chad McBride, Andrew Wottreng
Life of this patent
Estimating the term…
Abstract
The present invention provides an improved way to calculate a replacement way within a processor cache that is effective with different combinations of hardware address translation cache miss handling, software address translation cache miss handling, and hint lock bits. For some embodiments, LRU bits used to select an entry for replacement are updated only if software address translation cache miss handling is disabled. Further, for some embodiments, LRU bits may be modified to change the way a binary tree structure is traversed to avoid selecting a hint locked entry for replacement
Claims18
A method of updating entries in a table used to indicate recent use of entries in an address translation cache in order to guide replacement, comprising:
- detecting that a request for address translation hits in the address translation cache;
- determining if the request for address translation hit on a hint locked entry of the address translation cache;
- and
- updating an entry in the table only if the request for address translation hit on an entry that is not hint locked or software address translation cache miss handling is disabled.
A method of selecting an address translation cache entry for replacement, comprising:
- fetching data in response to an address translation request that misses in an address translation cache;
- retrieving an entry from a table;
- generating a selection value by modifying the retrieved table entry based on corresponding hint lock bits;
- and
- using the generated selection value to select a way in the cache for replacement with the fetched data.
A processor, comprising:
- an address translation cache;
- a table holding entries indicating the recent use of entries in the address translation cache;
- and
- logic configured to detect that a request for address translation hits in the address translation cache, determine if the request for address translation hit on a hint locked entry of the address translation cache, and update entries in the table only if the address translation cache hits on an entry that is not hint locked or software address translation cache miss handling is disabled.
The processor of claim. 9, wherein the logic is further configured to:
- the logic is further configured to retrieve an entry from the table and ignore the hint lock bits if all the hint lock bits indicate all the ways are hint locked and select a way for replacement based on an entry from the table.
A processor, comprising:
- an address translation cache;
- a table holding entries indicating the recent use of entries in the address translation cache;
- and
- logic configured to retrieve an entry from the table indicating recent use of entries in the cache, determine if the table entry would result in selection of a hint locked entry in the cache using a selection algorithm, and if so, modify one or more bits of the table entry in order to select a non-hint locked entry in the cache using the selection algorithm.
Dependencies are inferred from the claim text.