Symmetric multiprocessor system

A method for a symmetric multiprocessor (SMP) system, comprising:

• using a parent process to create a child process associated with each processor in the SMP;
• using each child process to configure a data event address register (DEAR) in a performance monitoring unit (PMU) for its associated processor in order to record cache misses that are not serviced by cache local to its associated processor;
• and
• recording DEAR information associated with each processor in a private array of a shared memory segment configured by the parent process.

A computer readable medium having executable instructions thereon for causing a symmetric multiprocessor (SMP) system to perform a method, comprising:

• using a parent process to create a child process associated with each processor in the SMP;
• using each child process to configure a data event address register (DEAR) in a performance monitoring unit (PMU) for its associated processor in order to record cache misses that are not serviced by cache local to its associated processor;
• running each child process when an associated DEAR signals that a cache miss record is available;
• using the associated child process to evaluate a signaling rate of the associated processor and adjust DEAR parameters to maintain a particular overhead rate;
• recording DEAR information associated with each processor in a private array of a shared memory segment configured by the parent process;
• and
• sending a termination signal from each child process to the parent process when a particular number of cache miss records have been recorded;
• and
• using the parent process to analyze the DEAR records associated with each processor, when a termination signal has been received from each child process.

A symmetric multiprocessor (SMP) system, comprising:

• a processor;
• a memory in communication with the processor;
• and
• program instructions storable in memory and executable by the processor to:
• create a child process for each processor in the SMP;
• use an event address register (EAR) associated with each processor to record information relating to cache misses;
• analyze the EAR records for each processor;
• and
• create a bit vector for each byte of cache line that is shared by multiple processors.

A symmetric multiprocessor (SMP) system, comprising:

• a processor;
• a memory in communication with the processor;
• and
• means for non obtrusively identifying true/false data sharing in the SMP without compiler inserted instrumentation or customer site instrumented software installation.