Time efficient embedded EEPROM/processor control method
AssigneeAtmel Corporation
InventorRandall Melton
Life of this patent
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Abstract
In an embedded system with a processor and an EEPROM that provides an EEPROM BUSY signal if the EEPROM is in a write mode, a block-before-write subroutine is used to hold the processor before a write operation to the EEPROM. A detector circuit finds read functions that are to be mapped into the EEPROM address space and suspends code execution if an EEPROM BUSY bit is asserted and the EEPROM is the read target. Code execution by the processor and processor access to memories other than the EEPROM is permitted while the EEPROM is being written. If any access is made by the processor to the EEPROM while the EEPROM BUSY bit is asserted, the processor enters a WAIT state to temporarily suspends execution of program code.
Claims10
A time-efficient read/write control method for an embedded EEPROM and processor, comprising the steps of:
- providing an EEPROM BUSY signal that is active when the EEPROM is engaged in a write activity;
- executing program code by the processor when the EEPROM BUSY signal is inactive;
- blocking write code execution by the processor at the start of a write subroutine when the EEPROM BUSY signal is active;
- blocking read code execution with a read detection circuit that detects when the EEPROM BUSY signal is active and when a read is requested for an EEPROM address;
- and
- continuing program code executing by the processor when the EEPROM BUSY signal is inactive, where the EEPROM BUSY signal blocks code execution such that write operations are blocked at the start of a write subroutine and such that read operations are blocked by the read detection circuit only when the read operations result in EEPROM read during an active EEPROM BUSY signal.
A time-efficient control method for an embedded EEPROM and processor, comprising the steps of:
- reading and writing the EEPROM with the processor;
- asserting an EEPROM BUSY signal by the EEPROM when the EEPROM is in a write mode of operation;
- using a block-before-write subroutine for the processor to suspend code execution by the processor if the EEPROM BUSY signal is asserted;
- detecting a read address that is mapped into the EEPROM address space;
- suspending code execution by the processor if a read address which is mapped into the address space of the EEPROM is detected and if the EEPROM BUSY signal is asserted;
- and
- allowing code execution by the processor and accesses by the processor to memory other than the EEPROM to continue as long as the EEPROM is not accessed by the processor and the EEPROM BUSY signal is not asserted.
Dependencies are inferred from the claim text.