System having bus architecture for improving CPU performance and method thereof

A system comprising:

• a main bus connected to a peripheral device;
• a first local bus connected to a memory device including a controller having an arbitration function and a memory core storing predetermined data;
• a second local bus connected between the main bus and the memory device;
• a first master capable of having an ownership of the main bus to access the peripheral device or an ownership of the first local bus to access the memory device;
• a second master connected to the main bus and capable of having an ownership of the main bus to access the peripheral device or an ownership of the second local bus to access the memory device;
• and
• a bridge connected to the main bus, the first master, and the memory device, the bridge monitoring whether the second master has the ownership of the main bus, decoding an address output from the first master, and outputting a first wait signal to the first master or outputting the address to one of the memory device and the peripheral device based on a monitoring result and a decoding result,
• wherein, when the first master and the second master simultaneously access the memory core, the controller permits access to the memory core to one of the first master and the second master and outputs a second wait signal to the other one of the first master and the second master