Apparatus for reissuing commands requiring access to a bus and methods of using the same

An apparatus for reissuing a command involving bus access, comprising:

• command reissuing logic having:
• a register;
• and
• an array coupled to the register;
• the command reissuing logic is adapted to:
• store information associated with commands that are to be reissued, wherein the commands are each associated with respective input/output (I/O) devices seeking bus access;
• store a count for each of the commands, each count indicating a number of times the associated command has been reissued;
• select a command to be reissued, from among the commands, based on the information associated with the command;
• and
• determine a delay after which the selected command will be reissued, wherein the delay is determined based on the count associated with the selected command.

A system, comprising:

• a processor;
• a plurality of input/output (I/O) devices;
• a bus, coupled to the I/O devices and the processor, and adapted to receive commands from the I/O devices and the processor;
• and
• an apparatus for reissuing a command involving bus access including:
• command reissuing logic having:
• a register;
• and
• an array coupled to the register;
• the command reissuing logic is adapted to:
• store information associated with commands that are to be reissued, wherein the commands are each associated with respective input/output (I/O) devices seeking bus access;
• store a count for each of the commands, each count indicating a number of times the associated command has been reissued;
• select a command to be reissued, from among the commands, based on the information associated with the command;
• and
• determine a delay after which the selected command will be reissued, wherein the delay is determined based on the count associated with the selected command.