Data structure traversal instructions for packet processing

A packet processor comprising:

• memory;
• and
• a packet processor core to:
• execute a data structure traversal instruction for use in packet processing, the data structure traversal instruction including a control;
• in response to the control of the data structure traversal instruction, the packet processor core to:
• traverse a data structure based upon input data from a source register;
• access at least one node of the data structure to obtain output data;
• and
• store the output data in a destination register.

A machine-readable medium having tangibly stored thereon a data structure traversal instruction, which when executed by a packet processor, causes the packet processor to perform the following operations:

• processing a control for use in packet processing;
• in response to the control,
• traversing a data structure based upon input data from a source register;
• accessing at least one node of the data structure to obtain output data;
• and
• storing the output data in a destination register.

A system comprising:

• a network device to couple a first network to a second network, the network device having a packet processor that includes:
• a packet processor core to:
• execute a data structure traversal instruction for use in packet processing, the data structure traversal instruction including a control;
• in response to the control of the data structure traversal instruction, the packet processor core to:
• traverse a data structure based upon input data from a source register;
• access at least one node of the data structure to obtain output data;
• and
• storing the output data in a destination register.