Copper Interconnect Wiring and Method and Apparatus for Forming Thereof
AssigneeTEL Epion Inc.
InventorsArthur Learn, Steven Sherman, Robert Geffken, John Hautala
Life of this patent
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Abstract
Capping layer or layers on a surface of a copper interconnect wiring layer for use in interconnect structures for integrated circuits and methods and apparatus for forming improved integration interconnection structures for integrated circuits by the application of gas-cluster ion-beam processing. Reduced copper diffusion and improved electromigration lifetime result and the use of selective metal capping techniques and their attendant yield problems are avoided. Various cluster tool configurations including gas-cluster ion-beam processing modules for copper capping, cleaning, etching, and film formation steps are disclosed.
Claims29
On a structure including one or more copper interconnect surfaces and one or more surfaces of a barrier layer material covering a dielectric material, a method of forming capping structures, comprising the steps of:
- disposing the structure in a reduced pressure chamber;
- forming an accelerated capping GCIB within the reduced pressure chamber;
- and
- directing the accelerated capping GCIB onto at least one of the one or more copper interconnect surfaces and onto at least one of the one or more surfaces of the barrier layer material covering the dielectric material, so as to form at least one capping structure on the one or more copper interconnect surfaces onto which the accelerated capping GCIB is directed.
On a structure including one or more copper interconnect surfaces and one or more dielectric surfaces, a method of forming capping structures, comprising the steps of:
- disposing the structure in a reduced pressure chamber;
- forming an accelerated capping GCIB within the reduced pressure chamber;
- and
- directing the accelerated capping GCIB onto at least one of the one or more copper interconnect surfaces and the one or more dielectric surfaces, so as to form at least one capping structure on the one or more surfaces onto which the accelerated capping GCIB is directed.
On an integrated circuit interconnection layer including one or more copper interconnect surfaces and one or more dielectric layer regions covered by barrier layer material, a method of forming a copper capping structure comprising the steps of:
- forming at least one capping structure on the one or more copper interconnect surfaces;
- and
- after forming the at least one capping structure on the one or more copper interconnect surfaces, removing the barrier layer material covering at least one of the one or more dielectric layer regions.
On an integrated circuit interconnection layer including one or more copper interconnect surfaces and one or more dielectric layer regions covered by barrier layer material, a method of forming a copper capping structure comprising the steps of:
- forming an accelerated capping GCIB using a first beam acceleration potential;
- directing the accelerated capping GCIB onto at least one of the one or more copper interconnect surfaces to form at least one capping structure on the one or more copper interconnect surfaces;
- forming an accelerated etching GCIB using a second beam acceleration potential less than the first beam acceleration potential;
- and
- directing the accelerated etching GCIB onto the at least one capping structure and onto the barrier layer material to remove the barrier layer material.
On an integrated circuit interconnection layer including one or more copper interconnect surfaces and one or more dielectric layer regions covered by barrier layer material, a method of forming a copper capping structure comprising the steps of:
- forming an accelerated capping GCIB;
- directing the accelerated capping GCIB onto at leas* one of the one or more copper interconnect surfaces to form at least one capping structure on the one or more copper interconnect surfaces;
- forming an accelerated etching GCIB;
- and
- directing the accelerated etching GCIB onto the at least one capping structure and onto the barrier layer material to remove the barrier layer material covering at least one of the one or more dielectric layer regions without removing all of the at least one capping structure.
Dependencies are inferred from the claim text.