Semiconductor devices including transistors having three dimensional channels and methods of fabricating the same

A semiconductor device comprising:

• a gate electrode crossing over a semiconductor fin on a semiconductor substrate;
• a gate insulating layer between the gate electrode and the semiconductor fin;
• a channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode;
• a doped region formed in the semiconductor fin at either side of the gate electrode;
• an interlayer insulating layer on a surface of the semiconductor substrate;
• and
• a connector region filling an opening, wherein the opening penetrates the interlayer insulating layer to expose at least a portion of an upper surface and both side surfaces of the doped region.

A method of forming a semiconductor device, the method comprising:

• forming a semiconductor fin on a semiconductor substrate;
• forming a gate insulating layer on a surface of the semiconductor fin;
• forming a gate conductive layer on the gate insulating layer;
• patterning the gate conductive layer to form a gate electrode crossing over the semiconductor fin;
• forming a doped region in the semiconductor fin at either side of the gate electrode;
• forming an interlayer insulating layer on a surface of the substrate;
• and
• forming a connector region in an opening to be connected to the doped region, the opening penetrating the interlayer insulating layer, wherein a recess region is formed in the doped region connected to the connector region and wherein the connector region contacts an inner surface of the recess region.

A method of forming a semiconductor device, the method comprising:

• forming a gate insulating layer on a semiconductor fin formed on a semiconductor substrate;
• forming a gate conductive layer on the gate insulating layer;
• patterning the gate conductive layer to form a gate electrode crossing over the gate semiconductor fin;
• forming a doped region on the semiconductor fin provided at either side of the gate electrode;
• forming an interlayer insulating layer on a surface of the semiconductor substrate;
• patterning the interlayer insulating layer to expose at least a portion of an upper surface and both side surfaces of the doped region;
• and
• forming a connector region filling an opening.