US 2007/0184622 A1 · High voltage transistor and method of manufacturing the same

Abstract

The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region having the channel region interposed therebetween and each being formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance that is larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; and a second metal silicide layer which is formed on the high concentration drain region.

Claims10

Dependent claims

A method of manufacturing a high voltage transistor, the method comprising:

forming a mask pattern covering a first region on a first conductive semiconductor substrate;
forming a gate insulating film on a surface of the semiconductor substrate exposed through the mask pattern;
forming a gate electrode asymmetrically extending from an upper surface of the gate insulating film to an upper surface of the mask pattern;
removing the mask pattern to expose the first region;
implanting a low concentration impurity having a second conductivity opposite to the first conductivity on the resultant semiconductor substrate such that a low concentration source region and a low concentration drain region are formed at both sides of the gate electrode;
forming each of asymmetric-structured first insulating spacer and second insulating spacer on both sidewalls of the gate electrode;
implanting with a high concentration impurity using the gate electrode, the first insulating spacer and the second insulating spacer as an implant mask to form a high concentration source region and a high concentration drain region;
and
forming a metal silicide layer on the high concentration source region and the high concentration drain region.

6 more elements

Dependencies are inferred from the claim text.

High voltage transistor and method of manufacturing the same

Life of this patent

High voltage transistor and method of manufacturing the same

Life of this patent

Abstract

Claims10