US 2007/0184621 A1 · MOSFET WTH HIGH ANGLE SIDEWALL GATE AND CONTACTS FOR REDUCED MILLER CAPACITANCE

Abstract

The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.

Claims8

Dependent claims

A method for fabricating an FET device, comprising:

forming a gate dielectric layer over a semiconductor substrate;
forming a gate conductor layer over the gate dielectric layer;
selectively patterning the gate conductor layer to form a conductive gate electrode that has a top, a base, and sidewalls, wherein the sidewalls of said conductive gate electrode are offset from a vertical direction by an offset angle that is greater than about 0° and not more than about 45°, so that the top of said conductive gate electrode has a surface area smaller than that of the base;
and
forming source and drain regions in the semiconductor substrate.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/694,225Filed 30 Mar 2007

Priority

9 Sep 2005

Published

9 Aug 2007

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 30/605
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having significant overlap between the lightly-doped extensions…
H10D 30/0212
Of FETs having insulated gates [IGFET]: using self-aligned silicidation
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 62/371
Of igfets: inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current

Mosfet wth high angle sidewall gate and contacts for reduced miller capacitance

Life of this patent

Mosfet wth high angle sidewall gate and contacts for reduced miller capacitance

Life of this patent

Abstract

Claims8