Loading patent…
AssigneeKoninklijke Philips Electronics N.V.
InventorBartlomiej Pawlak
Estimating the term…
The invention relates to a method of manufacturing a field effect transistor, in which method a semiconductor body (1) of silicon is provided at a surface thereof with a source region (2) and a drain region (3) of a first conductivity type, which regions are both provided with extensions (2A, 3A), and with a gate region (5) situated above the channel region (4), and wherein a pn-junction between the extensions (2A, 3A) and a neighboring part (4A) of the channel region (4) is formed by two implantations (I1, I2) of dopants of opposite conductivity type, and wherein before said two implantations (I1, I2) of dopants of opposite conductivity type an amorphizing implantation (I0) is performed where the pn-junction is to be formed. The amorphizing implantation (I0) and said two implantations (I1, I2) of dopants are both carried out before the gate region (5) is formed and at an angle with the surface of the semiconductor body (I) which is substantially equal to 90 degrees. In this way, the most relevant part of the pn-junction formed, i.e. the vertical part that runs perpendicularly to the surface, is not only very steep and abrupt but also has a very low leakage current due to the absence of implantations defects. Preferably, a low temperature anneal is used to regrow crystalline silicon.
Method of manufacturing a semiconductor device (10) comprising a field effect transistor, in which method a semiconductor body (1) of silicon is provided at a surface thereof with a source region (2) and a drain region (3) of a first conductivity type, which regions are both provided with extensions (2A,3A), and with a channel region (4) of a second conductivity type, opposite to the first conductivity type, between the source region (2) and the drain region (3), and with a gate region (5) separated from the surface of the semiconductor body (1) by a gate dielectric (6) and situated above the channel region (4), and wherein a pn-junction between the extensions (2A,3A) and a neighboring part (4A) of the channel region (4) is formed by two implantations (I1, I2) of dopants of opposite conductivity type, and wherein before both of said two implantations (I1, I2) of dopants of opposite conductivity type are performed an amorphizing implantation (I0) is performed where the pn-junction is to be formed, characterized in that the amorphizing implantation (I0) and said two implantations (I1, I2) of dopants of opposite conductivity type are performed before the gate region (5) is formed and at an angle with the surface of the semiconductor body (1) which is substantially equal to 90 degrees.
Dependencies are inferred from the claim text.