Process for Manufacturing a Non-Volatile Memory Electronic Device Integrated on a Semiconductor Substrate and Corresponding Device

A process for manufacturing an electronic device integrated on a semiconductor substrate comprising a plurality of non-volatile memory cells organized in a matrix of rows and columns, with wordlines coupled to the rows and bit lines coupled to the columns, and comprising circuitry associated therewith, the method comprising:

• forming gate electrodes projecting from the semiconductor substrate for the non-volatile memory cells, each gate electrode comprising a first dielectric layer, a floating gate electrode on the first dielectric layer, a second dielectric layer on the floating gate electrode and a control gate electrode on the second dielectric layer, the control gate electrode being coupled to a respective wordline, and at least a first portion of the gate electrodes being separated from each other by a first opening having a first width;
• forming source and drain regions in the semiconductor substrate for the memory cells, with the source and drain regions being aligned with the gate electrodes of the memory cells;
• forming gate electrodes projecting from the semiconductor substrate for transistors of the circuitry associated with the plurality of non-volatile memory cells, each gate electrode comprising a first dielectric layer and a first conductive layer thereon;
• forming source and drain regions in the semiconductor substrate for the transistors of the circuitry, with the source and drain regions being aligned with the gate electrodes of the transistors;
• and
• depositing a third dielectric layer on the gate electrodes and on the source and drain regions while not completely filling in the first openings so that air-gaps are formed between the gate electrodes of the at least first portion of the gate electrodes.

A process for manufacturing an electronic device comprising:

• forming a plurality of non-volatile memory cells organized in a matrix of rows and columns on a semiconductor substrate;
• forming wordlines coupled to the rows and forming bit lines coupled to the columns of the non-volatile memory cells;
• forming the plurality of memory cells comprising
• forming gate electrodes projecting from the semiconductor substrate, each gate electrode comprising a first dielectric layer, a floating gate electrode on the first dielectric layer, a second dielectric layer on the floating gate electrode and a control gate electrode on the second dielectric layer, the control gate electrode being coupled to a respective wordline, and at least a first portion of the gate electrodes being separated from each other by a first opening having a first width, and
• forming source and drain regions in the semiconductor substrate for the memory cells, with the source and drain regions being aligned with the gate electrodes of the memory cells;
• forming circuitry on the semiconductor substrate comprising transistors associated with the plurality of non-volatile memory cells, the forming comprising
• forming gate electrodes projecting from the semiconductor substrate for the transistors, each gate electrode comprising a first dielectric layer and a first conductive layer thereon, and
• forming source and drain regions in the semiconductor substrate for the transistors, with the source and drain regions being aligned with the gate electrodes of the transistors;
• and
• depositing a third dielectric layer on the gate electrodes and on the source and drain regions while not completely filling in the first openings so that air-gaps are formed between the gate electrodes of the at least first portion of the gate electrodes.

An electronic device comprising:

• a semiconductor substrate;
• a plurality of non-volatile memory cells organized as a matrix of rows and columns on said semiconductor substrate;
• wordlines coupled to the rows, and bit lines coupled to the columns of said matrix of memory cells;
• circuitry on said semiconductor substrate and associated with said plurality of non-volatile memory cells;
• each memory cell comprising:
• a gate electrode projecting from said semiconductor substrate and comprising a first dielectric layer, a second dielectric layer on said floating gate electrode, and a control gate electrode on said second dielectric layer, said control gate electrode being coupled to a respective wordline, and
• source and drain regions on said semiconductor substrate and aligned with said gate electrode;
• and
• a third dielectric layer on at least one portion of said gate electrodes being insulated from each other by first air-gaps which are closed on top by said third dielectric layer.