Method of forming semiconductor device

A method of forming a semiconductor device, the method comprising:

• preparing a substrate including a cell region, a low voltage region and a high voltage region;
• forming a high-voltage gate insulating layer on the high voltage region;
• forming a tunnel insulating layer on the cell and low voltage regions;
• forming a first charge storage gate pattern, a second charge storage gate pattern and a third charge storage gate pattern on a portion of the tunnel insulating layer on the cell region, on a portion of the tunnel insulating layer on the low voltage region and on the high-voltage gate insulating layer, respectively;
• forming a blocking insulating layer and a control gate conductive layer on each of the first, second and third charge storage gate patterns;
• selectively removing portions of the control gate conductive layer and portions of the blocking insulating layer on the low and high voltage regions with respect to portions of the control gate conductive layer and the blocking insulating layer on the cell region;
• removing the second charge storage gate pattern and the portion of the tunnel insulating layer on the low voltage region, thereby exposing a portion of the low voltage region;
• forming a low voltage gate insulating layer on the exposed portion of the low voltage region;
• and
• forming a low-voltage gate conductive pattern on the low-voltage gate insulating layer.

A method of forming a semiconductor device, the method comprising:

• preparing a substrate including a cell region, a low voltage region, a high voltage region and a resistor region;
• forming a high-voltage gate insulating layer on the high voltage region;
• forming a tunnel insulating layer on the cell and low voltage regions;
• forming a first charge storage gate pattern, a second charge storage gate pattern and a third charge storage gate pattern on a portion of the tunnel insulating layer on the cell region, on a portion of the tunnel insulating layer on the low voltage region and on the high-voltage gate insulating layer, respectively;
• forming a blocking insulating layer and a control gate conductive layer on each of the first, second and third charge storage gate patterns and on the resistor region;
• selectively removing portions of the control gate conductive layer and the blocking insulating layer on the low and high voltage regions with respect to portions of the control gate conductive layer and the blocking insulating layer on the cell region;
• removing the second charge storage gate pattern and the portion of the tunnel insulating layer on the low voltage region, thereby exposing a portion of the low voltage region;
• forming a low voltage gate insulating layer on the exposed portion of the low voltage region;
• and
• forming a low-voltage gate conductive pattern on the low-voltage gate insulating layer.