Method of forming a semiconductor device

A method for forming a semiconductor device comprising:

• providing a semiconductor substrate having a first doped region and a second doped region;
• providing a dielectric over the first doped region and the second doped region;
• providing a metal layer over the dielectric;
• patterning the metal layer to leave a metal portion over at least a portion of the first doped region;
• forming an in situ doped semiconductor layer over the metal portion and the second doped region;
• forming a blocking capping layer over the in situ doped semiconductor layer;
• patterning the blocking capping layer, in situ doped semiconductor layer, and the metal portion to leave a semiconductor gate over the second doped region and a metal/semiconductor gate stack over the first doped region having an in situ doped semiconductor portion and a blocking cap;
• and
• performing an implant to form deep source/drain regions adjacent the metal/semiconductor gate stack, wherein the blocking cap has a thickness sufficient to block dopants from the implant from entering the in situ doped semiconductor portion.

A method for forming a semiconductor device comprising:

• providing a semiconductor substrate having a first doped region and a second doped region;
• providing a dielectric over the first doped region and the second doped region;
• forming a first gate stack over the dielectric over at least a portion of the first doped region, the first gate stack having a metal portion over the dielectric, and a first in situ doped semiconductor portion over the metal portion;
• forming a second gate stack over the dielectric over at least a portion of the second doped region, the second gate stack having a second in situ doped semiconductor portion over the dielectric;
• forming first stressor source/drain regions adjacent the first gate stack, wherein the first stressor source/drain regions provide stress to a first channel region in the semiconductor substrate under the first gate stack;
• and
• forming second stressor source/drain regions adjacent the second gate stack, wherein the second stressor source/drain regions provide stress to a second channel region in the semiconductor substrate under the second gate stack.