Stress liner for integrated circuits
AssigneeCypress Semiconductor Corporation
InventorsIgor Polishchuk, Krishnaswamy Ramkumar, Sagy Levy
Life of this patent
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Abstract
In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.
Claims20
A method of forming an integrated circuit structure, the method comprising:
- forming a gate of a first MOS transistor over a substrate;
- forming active regions of the first MOS transistor in the substrate;
- forming a stress liner over the gate and active regions of the first MOS transistor, the stress liner imparting strain on the substrate to increase a drive current of the first MOS transistor;
- forming a dielectric layer over the gate and the active regions of the first MOS transistor;
- and
- forming a trench structure over each of the active regions of the first MOS transistor through the dielectric layer such that each of the active regions of the first MOS transistor is exposed for an electrical connection and portions of the stress liner over each of the active regions of the first MOS transistor are removed.
An integrated circuit structure comprising:
- a first MOS transistor comprising a gate, a gate oxide under the gate, a substrate under the gate oxide, and active regions in the substrate;
- a second MOS transistor comprising a gate, a gate oxide under the gate, the substrate under the gate oxide, and active regions in the substrate, the first and second MOS transistors forming a complementary pair of MOS transistors;
- a dielectric layer formed over the gate and active regions of both the first and second MOS transistors.
- a stress liner formed over the gate and active regions of the first MOS transistor, the same stress liner also being formed over the gate and active regions of the second MOS transistor;
- and
- a self-aligned contact (SAC) trench structure formed over each of the active regions of the first MOS transistor through the dielectric layer such that each of the active regions of the first MOS transistor is exposed.
A method of forming an integrated circuit structure, the method comprising:
- forming a gate of a first MOS transistor and a second MOS transistor, the first and second MOS transistors being a complementary pair of MOS transistors;
- forming spacers on sidewalls of the gates of the first and second MOS transistors;
- forming active regions of the first and second MOS transistors using the spacers for alignment;
- removing the spacers from the sidewalls of the gates of the first and second MOS transistors;
- forming a same stress liner over the gates and active regions of the first and second MOS transistors, the stress liner imparting strain on the substrate;
- forming a dielectric layer over the gates and active regions of the first and second MOS transistors;
- and
- forming a self-aligned contact (SAC) trench structure over each of the active regions of the first and second MOS transistors through the dielectric layer, the SAC trench structure removing substantial portions of the stress liner over an underlying active region and exposing the underlying active region.
Dependencies are inferred from the claim text.