US 2007/0184588 A1 · WRAP-AROUND GATE FIELD EFFECT TRANSISTOR

Abstract

A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

Claims19

Dependent claims

A method for forming a wrap-around-gate field-effect transistor on a handle wafer, the method comprising:

forming a silicon-on-insulator (SOI) structure on the handle wafer, the SOI structure including a silicon island between a first oxide layer and a second oxide layer;
creating a cavity in the SOI structure extending from a top surface of the SOI structure to the handle wafer, the cavity having substantially vertical sidewalls and intersecting the silicon island;
isotropically etching the first oxide layer and the second oxide layer within the cavity thereby exposing surface portions of the silicon island;
depositing a gate conductor material on the surface portions;
and
isotropically etching the gate conductor material to form a wrap-around gate electrode circumscribing a periphery of the silicon island.

3 more elements

Dependencies are inferred from the claim text.

Wrap-around gate field effect transistor

Life of this patent

Wrap-around gate field effect transistor

Life of this patent

Abstract

Claims19