Method of fabrication on high coplanarity of copper pillar for flip chip packaging application

Abstract

This invention is characteristic of combining an electroplating process with a polishing process to uniformly fabricate multi-layer flip chip copper pillar. All kinds of flip chip copper pillar with varied shapes and sizes are able to be defined by using multi-layer photolithography process commonly utilized in the semiconductor processes. After that, use both exposure and alignment procedures to accurately define multi-layer photoresist's patterns on the substrate. Some designated metallic materials are then electroplated on those completed well-defined patterns during the last photolithography process by means of an electroplating process. A polishing process follows the electroplating to level the rugged solder bumps, resulted from the impact on the certain changeable and inevitable electroplating parameters. The first layer of evenly polished flip chip copper pillar could be used as a base metal to continuously deposit another separate flip chip copper pillar that may have different materials as well as heights from the first one. Similarly, the second upper layer of flip chip copper pillar is capable of being uniformly polished employing the same polishing mechanism as the first one. High coplanarity of multi-layer electroplating-based flip chip copper pillar suitable to be used in the high-end and advanced three-dimensional electronic packaging will be achieved after finishing the final reflow process.

Dependencies are inferred from the claim text.