Clock and data recovery circuit having gain control
AssigneeInfineon Technologies AG
InventorsAnthony Sanders, Dirk Scheideler, Edoardo Prete
Life of this patent
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Abstract
A clock and data recovery circuit includes a phase detector configured to compare a phase of a data signal to a phase of a sampling clock to provide a phase error signal, a gain stage configured to apply a gain to the phase error signal to provide an amplified phase error signal, and a filter configured to filter the amplified phase error signal to provide a phase correction signal. The circuit includes a gain controller configured to adjust the gain of the gain stage in response to the phase correction signal, and a clock generator configured to provide the sampling clock based on the phase correction signal.
Claims25
A clock and data recovery circuit comprising:
- a phase detector configured to compare a phase of a data signal to a phase of a sampling clock to provide a phase error signal;
- a gain stage configured to apply a gain to the phase error signal to provide an amplified phase error signal;
- a filter configured to filter the amplified phase error signal to provide a phase correction signal;
- a gain controller configured to adjust the gain of the gain stage in response to the phase correction signal;
- and
- a clock generator configured to provide the sampling clock based on the phase correction signal.
An advanced memory buffer comprising:
- a clock and data recovery circuit configured to adjust a gain of the clock and data recovery circuit based on a phase correction signal of the clock and data recovery circuit to maintain stability during high data transition density and to fulfill slew rate requirements during low data transition density.
A clock and data recovery circuit comprising:
- means for determining a phase error between a data signal and a sampling clock to provide a phase error signal;
- means for applying a gain to the phase error signal to provide an amplified phase error signal;
- means for filtering the amplified phase error signal to provide a phase correction signal;
- means for adjusting the gain in response to the phase correction signal;
- and
- means for providing the sampling clock based on the phase correction signal.
A method for recovering a clock signal and data, the method comprising:
- determining a phase difference between a data signal and a sampling clock to provide a phase error signal;
- applying a gain to the phase error signal to provide an amplified phase error signal;
- filtering the amplified phase error signal to provide a phase correction signal;
- adjusting the gain in response to the phase correction signal;
- and
- providing the sampling clock based on the phase correction signal.
A method for recovering a clock signal and data, the method comprising:
- providing a clock and data recovery circuit having a gain stage and a gain controller;
- reducing the gain of the gain stage to a first predetermined value in response to a phase correction event received by the gain controller;
- and
- gradually increasing the gain of the gain stage to a second predetermined value in response to the gain controller not receiving any phase correction events.
The method of claim 24, wherein reducing the gain of the gain stage comprises reducing the gain of the gain stage to a maximum gain for circuit stability.
The method of claim 24, wherein gradually increasing the gain of the gain stage comprises gradually increasing the gain of the gain stage to a minimum gain to meet slew rate requirements.
Dependencies are inferred from the claim text.