Method and circuit for obtaining asynchronous demapping clock

An asynchronous demapping circuit, wherein the asynchronous demapping circuit comprises:

• a smoothing control module, which is adapted to receive data to be demapped and a corresponding clock signal, and obtain and output a smoothed clock with even gaps in accordance with the data to be mapped and the corresponding clock signal;
• a phase locking module, which is adapted to perform phase locking to the smoothed clock with even gaps input from the smoothing control module in accordance with a signal reflecting writing and reading conditions of data of a secondary First In First Out (FIFO) so as to obtain a demapping clock;
• a writing control module, which is adapted to receive data to be demapped and corresponding clock signal, and output a gapped clock as a writing clock of a primary FIFO;
• the primary FIFO, which is adapted to receive the data to be demapped which are written into the primary FIFO in accordance with the gapped clock output from the writing control module and control the reading of data from the primary FIFO by utilizing a smoothed clock output from a smoothing control module as a reading clock;
• the secondary FIFO, which is adapted to receive the data output from the primary FIFO, wherein the smoothed clock output from the smoothing control module is utilized as a writing clock of the secondary FIFO, the secondary FIFO is connected to a phase locking module, and is adapted to send positions of writing and reading pointers of the secondary FIFO to the phase locking module, so as to enable the phase locking module to perform phase locking in accordance with the positions of writing and reading pointers, to obtain a reading clock for the secondary FIFO to control the reading of demapped data from the secondary FIFO.

An asynchronous demapping circuit, wherein the asynchronous demapping circuit comprises:

• a smoothing control module, which is adapted to receive data to be demapped and a corresponding clock signal, and obtain and output a smoothed clock with even gaps in accordance with the data to be mapped and the corresponding clock signal;
• a phase locking module, which is adapted to perfonm phase locking to the smoothed clock with even gaps input from the smoothing control module in accordance with a signal reflecting writing and reading conditions of data of a First In First Out (FIFO) so as to obtain a demapping clock;
• a writing control module, which is adapted to receive the data to be demapped and a corresponding clock signal, and output a gapped clock as a writing clock for the FIFO;
• the FIFO, which is adapted to receive the data to be demapped which are written into the FIFO in accordance with the gapped clock from the writing control module and control the reading of demapped data from the FIFO by utilizing the demapping clock output from the phase locking module as a reading clock of the FIFO.