Multi-pair gigabit ethernet transceiver having adaptive disabling of circuit elements

An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

• measurement circuitry configured to measure a performance degradation characteristic resulting from disabling each member of a set of sub-pluralities of a plurality of circuit elements;
• disabling circuitry configured to adaptively disable one or more of the sub-pluralities of the circuit elements until the performance degradation characteristic reaches a threshold level;
• and
• a single state decision feedback equalizer;

An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

• a single state decision feedback equalizer having a set of ordered coefficients, the decision feedback equalizer defining a coefficient related tail value and a low order subset of coefficient values;
• a state multiplication circuit, the state multiplication circuit expanding a single state representation output signal received from the single state decision feedback equalizer into an N state representation signal suitable for decoding by the DFSE;
• a first ISI compensation circuit receiving an input signal and outputting a second signal substantially compensated for a first ISI component;
• and
• a second ISI compensation circuit, the second ISI compensation circuit receiving the second signal and generating a third signal, the third signal being substantially compensated for a second ISI component.

An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

• measurement circuitry configured to measure a performance degradation characteristic resulting from disabling each member of a set of sub-pluralities of a plurality of circuit elements;
• disabling circuitry configured to adaptively disable one or more of the sub-pluralities of the circuit elements until the performance degradation characteristic reaches a threshold level;
• and
• a first ISI compensation circuit configured to compensate for a transmitter induced ISI component;
• and
• a second ISI compensation circuit configured to compensate for a transmission channel induced ISI component.

An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

• measurement circuitry configured to measure a performance degradation characteristic resulting from disabling each member of a set of sub-pluralities of a plurality of circuit elements;
• disabling circuitry configured to adaptively disable one or more of the sub-pluralities of the circuit elements until the performance degradation characteristic reaches a threshold level;
• and
• a decoder system for computing the distance of a received symbolic word from a codeword.

An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

• a first ISI compensation circuit configured to compensate for a transmitter induced ISI component;
• a second ISI compensation circuit configured to compensate for a transmission channel induced ISI component;
• and
• a decoder system for computing the distance of a received symbolic word from a codeword.

An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

• a decision feedback sequence estimation (DFSE) circuit, for decoding an input sample into a final decision corresponding to a codeword of a trellis code having N states, the DFSE including a single state decision feedback equalizer;
• a first ISI compensation circuit configured to compensate for a transmitter induced ISI component;
• a second ISI compensation circuit configured to compensate for a transmission channel induced ISI component;
• and
• adaptive circuitry for reducing power consumption of a filter, the filter having an initial set of active coefficients, an input and an output, the active coefficients being ordered, a lowest ordered active coefficient of the initial set being proximal to the input, each of the active coefficients having a stable value.

An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

• measurement circuitry configured to measure a performance degradation characteristic resulting from disabling each member of a set of sub-pluralities of a plurality of circuit elements;
• disabling circuitry configured to adaptively disable one or more of the sub-pluralities of the circuit elements until the performance degradation characteristic reaches a threshold level;
• a single state decision feedback equalizer;
• a first ISI compensation circuit configured to compensate for a transmitter induced ISI component;
• a second ISI compensation circuit configured to compensate for a transmission channel induced ISI component;
• and
• a decoder system for computing the distance of a received symbolic word from a codeword.

A method for reducing effect of switching noise in a system, the system comprising a set of subsystems, each of the subsystems comprising an analog section and a digital section, each of the analog sections operating in accordance with a corresponding one of a set of sampling clock signals, the digital sections operating in accordance with a receive clock signal, the method comprising the operations of:

• generating the sampling clock signals such that the sampling clock signals are synchronous in frequency with each other;
• generating the receive clock signal such that the receive clock signal is synchronous in frequency with the sampling clock signals and having a phase offset with respect to one of the sampling clock signals;
• and
• adjusting the phase offset such that effect of switching noise from the digital sections on the analog sections is substantially minimized.

A method for generating a set of clock signals in a system, the set of clock signals comprising a set of sampling clock signals, the system comprising a set of subsystems, each of the subsystems comprising an analog section, each of the analog sections operating in accordance with a corresponding one of the sampling clock signals, the method comprising the operations of:

• generating a phase error for each of the sampling clock signals from a corresponding phase detector;
• inputting each of the phase errors to a corresponding loop filter;
• generating filtered phase errors from the corresponding loop filters;
• inputting each of the filtered phase errors to a corresponding oscillator;
• generating phase control signals from the corresponding oscillators;
• inputting each of the phase control signals to a corresponding phase selector;
• and
• generating the sampling clock signals from the corresponding phase selectors.

A timing recovery system for generating a set of clock signals in a processing system, the set of clock signals comprising a set of sampling clock signals, the processing system comprising a set of processing subsystems, each of the processing subsystems comprising an analog section, each of the analog sections operating in accordance with a corresponding one of the sampling clock signals, the timing recovery system comprising:

• (a) a set of phase detectors generating phase errors for the corresponding sampling clock signals;
• (b) a set of loop filters coupled to the corresponding phase detectors, the loop filters receiving the corresponding phase errors and generating filtered phase errors;
• (c) a set of oscillators coupled to the corresponding loop filters, the oscillators receiving the filtered phase errors and generating phase control signals;
• and
• (d) a set of phase selectors coupled to the corresponding oscillators, the phase selectors receiving the phase control signals and generating the sampling clock signals.

A timing recovery system for generating a set of clock signals in a processing system, the set of clock signals comprising a set of sampling clock signals, the processing system comprising a set of processing subsystems, each of the processing subsystems comprising an analog section, each of the analog sections operating in accordance with a corresponding one of the sampling clock signals, the timing recovery system comprising:

• (a) a set of phase detectors generating phase errors for the corresponding sampling clock signals;
• (b) a set of loop filters coupled to the corresponding phase detectors, the loop filters receiving the corresponding phase errors and generating filtered phase errors;
• (c) a set of digital-to-analog (D/A) converters coupled to the loop filters, the D/A converters receiving the filtered phase errors and generating analog filtered phase errors;
• and
• (d) a set of oscillators coupled to the corresponding D/A converters, the oscillators receiving the analog filtered phase errors and generating the sampling clock signals.