Viterbi decoding circuit and wireless device

A Viterbi decoding circuit comprising:

• a setting register in which parameters are changeably set according to a type of wireless communication standard, the parameters including a code rate, a constraint length, and a generator polynomial;
• a branch metric calculating unit configured to calculate a branch metric of an input signal and to generate branch metric information in an amount according to the code rate;
• a replica generating unit configured to replicate, based on the generator polynomial, a specification of an encoder at a transmitting-end, and to generate setting information related to selection of the branch metric information;
• a branch metric selection unit configured to perform selection of an upper branch metric and a lower branch metric from among a plurality of pieces of the branch metric information, based on the setting information;
• an add-compare-select unit configured to determine a path metric for each step in a trellis diagram based on the upper branch metric and the lower branch metric, and to determine a surviving branch and a path metric value;
• a path memory unit configured to store the surviving branch and the path metric value;
• and
• a trace back unit configured to read out the surviving branch from the path memory unit, and to determine the shortest path metric by tracing back a trellis path in the trellis diagram.