Symmetrical data signal processing

A digital communications receiver for receiving a VSB signal representing a sequence of encoded symbols each representative of a plurality of data bits, the receiver comprising:

• an input configured to receive a VSB signal from a communications channel;
• an amplification and filtration device coupled to the input and configured to adjust a magnitude of, and to filter, the VSB signal to produce a scaled and filtered VSB signal;
• and
• a virtual sub-carrier estimator coupled to the amplification and filtration device and configured to process the scaled and filtered VSB signal to estimate virtual sub-carriers such that the virtual sub-carriers are conjugate symmetric.

An integrated circuit chip for receiving and processing a VSB signal representing a sequence of encoded symbols each representative of a plurality of data bits, the chip comprising:

• an input configured to receive a VSB signal from a communications channel;
• front-end processing circuitry coupled to the input and configured to alter characteristics of the VSB signal to produce a modified signal having a desired format;
• and
• virtual sub-carrier estimator circuitry coupled to the front-end processing circuitry and configured to process the modified signal to estimate virtual sub-carriers such that the virtual sub-carriers are conjugate symmetric.