High speed, low power, low leakage read only memory
AssigneeSTMicroelectronics Pvt. Ltd.
InventorYogesh Luthra
Life of this patent
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Abstract
A read only memory (ROM) for providing a high operational speed with reduced leakage and low power consumption. The read only memory (ROM) includes multiple bit lines, multiple word lines, multiple column select lines and these lines are operatively coupled with multiple transistors. The arrangement of the ROM is such that the word line of a selected row is pulled down to a ground voltage (Vgnd). Non-selected word lines are kept at a supply voltage VDD to ensure that unwanted rows will not have any sub-threshold current (as Vds=0). So during read “1” operation (that is when bit line (BL) is high) load cells would not leak unnecessarily. Thus the ROM achieves a high operational speed with reduced leakage and low power consumption.
Claims20
A read only memory (ROM) having high operational speed with reduced leakage and low power consumption, the ROM comprising:
- a plurality of bit lines;
- a plurality of word lines;
- a plurality of column select lines;
- and
- a plurality of transistors operatively coupled to the bit lines, the word lines and the column select lines, each one of the transistors comprising:
- a source terminal connected to a selected one of the word lines;
- a drain terminal connected to a selected one of the bit lines;
- and
- a gate terminal connected to a selected one of the column select lines, wherein the word line is connected to a ground voltage and the column select line is connected to a supply voltage.
A method of building a read only memory (ROM) having a high operational speed with reduced leakage and low power consumption, the method comprising:
- coupling a plurality of transistors to a plurality of word lines, a plurality of bit lines and a plurality of column select lines in the ROM to reduce one or more cross talks;
- connecting one of the word lines to a source of a selected one of the transistors;
- connecting one of the bit lines to a drain of the selected transistor;
- and
- connecting one of the column select lines to a gate of the selected transistor, such that the word line is connected to a ground voltage and the column select line is connected to a supply voltage.
A read only memory (ROM) comprising:
- a plurality of bit lines;
- a plurality of word lines;
- a plurality of column select lines;
- and
- a plurality of transistors operatively coupled to the bit lines, the word lines and the column select lines, wherein each one of the transistors have a source terminal connected to a selected one of the word lines, a drain terminal connected to a selected one of the bit lines, a gate terminal connected to a selected one of the column select lines,
- wherein the word line is connected to a ground voltage and the column select line is connected to a supply voltage to provide high operational speed with reduced leakage and low power consumption.
Dependencies are inferred from the claim text.