Bank controller, information processing device, imaging device, and controlling method

An imaging device comprising:

• (a) an imaging section;
• (b) a synchronous DRAM;
• and
• (c) a bank controller that controls communication to banks of said synchronous DRAM,
• said bank controller comprising:
• (c-1) a plurality of processing blocks each having at least one FIFO memory that is associated with one of said banks of said synchronous DRAM and capable of performing data communication with the associated bank, said plurality of processing blocks performing predetermined operations with data stored in said FIFO memories;
• and
• (c-2) a memory interface that controls said data communication,
• said memory interface comprising:
• a priority order determining block that determines an order of priorities in said data communication between said FIFO memories and the associated banks;
• and
• a memory controller that implements the data communication between one of said FIFO memories that is assigned a high priority in said data communication and the associated bank,
• wherein said plurality of processing blocks include an image input block that at least performs operations of temporarily storing image data captured by said imaging section into its own said FIFO memory and sending the image data to said synchronous DRAM, and
• said priority order determining block determines said order of priorities among said FIFO memories at least on the basis of (1) information about states of precharge of said banks, and (2) information about channel numbers assigned to said FIFO memories, where these pieces of information are referred to in this order of precedence,
• and wherein the channel number assigned to the FIFO memory of said image input block is set such that the FIFO memory of said image input block is assigned a highest priority when pieces of information other than the information about the channel numbers are in same conditions.

A method of controlling data communication performed between banks of a synchronous DRAM and a bank controller, said bank controller comprising a plurality of processing blocks each having at least one FIFO memory that is associated with one of said banks of said synchronous DRAM and capable of performing data communication with the associated bank, said method comprising the steps of:

• (a) applying predetermined operations to data stored in said FIFO memories;
• (b) determining an order of priorities in the data communication between said FIFO memories and the associated banks;
• and
• (c) implementing the data communication between one of said FIFO memories that is assigned a high priority in said data communication and the associated bank,
• wherein said step (b) determines said order of priorities in said data communication at least on the basis of states of precharge of said banks.