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US 2007/0183242 A1Published application
Memory
AssigneeSanyo Electric Co., Ltd.
InventorHideaki Miyamoto
Life of this patent
Estimating the term…
Abstract
A memory capable of suppressing increase in circuit size, reduction in a period for an original access and increase in power consumption while suppressing an imprint can be obtained. The memory includes a first count detection circuit for detecting an access frequency with respect to memory cells, a second count detection circuit for detecting an access frequency of each of memory cell blocks and a third count detection circuit detecting a no-access frequency resulting in an imprint.
Claims17
A memory comprising:
- a plurality of memory cell blocks each including a plurality of memory cells;
- a refresh control circuit for performing a read operation and a rewrite operation with respect to said memory cells;
- a first count detection circuit for detecting an access frequency with respect to said memory cells;
- a second count detection circuit for detecting an access frequency of each said memory cell block;
- and
- a third count detection circuit detecting a frequency in which the sum of access frequencies of each said memory cell block counted by said second count detection circuit has not reached a prescribed frequency when said first count detection circuit detects that the sum of access frequencies with respect to said memory cells reaches a prescribed frequency.
3 more elements
Dependencies are inferred from the claim text.